Method for fabricating semiconductor device and semiconductor device using the same
View Patent ↗A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a channel ion implantation layer by an implantation of arsenic ions in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation. The implantation may be a low-density implantation of 1.0×10 12 ˜1.5×10 13 atoms/cm 2 performed at an energy level of 10˜100keV.
1. A method for fabricating a semiconductor device, comprising:
forming a device isolation layer defining an active area in a semiconductor substrate;
forming a channel ion implantation layer by an implantation of arsenic ions (As + ) in a predetermined region of the active area of the semiconductor substrate at a predetermined density; and
activating the channel ion implantation layer by annealing in a nitrogen (N 2 ) gas ambient of 1.025° C. using a rapid thermal annealing technique.
2. The method of claim 1 , wherein the channel ion implantation layer has a controlled doping profile according to the predetermined density of arsenic ion implantation.
3. The method of claim 1 , wherein the implantation is a low-density implantation of 1.0×10 12 ˜1.5×10 13 atoms/cm 2 .
4. The method of claim 3 , wherein the low-density implantation is performed at an energy level of 10˜100 keV.
5. The method of claim 1 , wherein the implantation is a low-density implantation of 1.82×10 13 atoms/cm 2 .
6. The method of claim 5 , wherein the low-density implantation is performed at an energy level of 110 keV.
7. The method of claim 1 , further comprising:
forming a photoresist pattern for exposing the predetermined region of the active area of the semiconductor substrate; and
using the photoresist pattern as a mask when implanting the arsenic ions.
8. The method of claim 1 , further comprising:
forming a gate on the semiconductor substrate to be disposed above the channel ion implantation layer; and
using the gate as mask to form a source/drain region in the semiconductor substrate.
9. The method of claim 8 , wherein the gate used as a mask includes sidewall spacers.
10. The method of claim 8 , farther comprising:
completing a pMOS transistor by forming, subsequent to the gate formation,
a cobalt salicide layer,
an interlayer dielectric material, and
a metallization layer.
11. A method for fabricating a semiconductor device, comprising:
forming a device isolation layer defining an active area in a semiconductor substrate;
forming a channel ion implantation layer by an implantation of arsenic ions (As + ) in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation,
wherein the predetermined doping profile is achieved by a low-density implantation of 1.0×10 12 ˜1.5×10 13 atoms/cm 2 ; and
activating the channel ion implantation layer by annealing in a nitrogen (N 2 ) gas ambient of 1.025° C. using a rapid thermal annealing technique.
12. The method of claim 11 , wherein the low-density implantation is performed at an energy level of 10˜100 keV.
13. A method for fabricating a semiconductor device, comprising:
forming a device isolation layer defining an active area in a semiconductor substrate;
forming a channel ion implantation layer by an implantation of arsenic ions (As + ) in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation,
wherein the predetermined doping profile is achieved by a low-density implantation of 1.82×10 13 atoms/cm 2 ; and
activating the channel ion implantation layer by annealing in a nitrogen (N 2 ) gas ambient of 1.025° C., using a rapid thermal annealing technique.
14. The method of claim 13 , wherein the low-density implantation is performed at an energy level of 100 keV.
15. A semiconductor device, comprising:
a semiconductor substrate;
a device isolation layer defining an active area in the semiconductor substrate; and
a channel ion implantation layer formed by an implantation of arsenic ions (As + ) in a predetermined region of the active area of the semiconductor substrate at a predetermined density,
wherein the channel ion implantation layer has a controlled doping profile according to the predetermined density of arsenic ion implantation and is activated by annealing in a nitrogen (N 2 ) gas ambient of 1,025° C. using a rapid thermal annealing technique.
16. The semiconductor device of claim 15 , wherein the implantation is a low-density implantation of 1.0×10 12 ˜1.5×10 13 atoms/cm 2 .
17. The semiconductor device of claim 16 , wherein the low-density implantation is performed at an energy level of 10˜100 keV.
18. The semiconductor device of claim 15 , wherein the implantation is a low-density implantation of 1.82×10 13 atoms/cm 2 .
19. The semiconductor device of claim 18 , wherein the low-density implantation is performed at an energy level of 110 keV.
20. The semiconductor device of claim 15 , wherein the semiconductor device is pMOS transistor.