IP Library Granted Patent US 7,071,080
Granted Patent B2
US 7,071,080 · App. 11/174,908 · Granted Jul 4, 2006

Process for producing silicon on insulator structure having intrinsic gettering by ion implantation

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Quick Facts
Patent No.
US 7,071,080
App. No.
11/174,908
Granted
Jul 4, 2006
Kind
B2
Abstract

The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Claims (48)

1. A process for producing a silicon on insulator structure, the structure comprising a silicon substrate having two major, generally parallel surfaces, one of which is the front surface and the other of which is the back surface, a central plane between the front and back surfaces, a surface layer which comprises a first region of the substrate between the front surface and a distance, D 1 , of at least about 10 micrometers as measured from the front surface and toward the central plane, and a bulk layer which comprises a second region of the substrate between the central plane and the first region, a circumferential edge joining the front and back surfaces, a central axis, and a radius extending from the central axis to the circumferential edge, the process comprising:

implanting oxygen into the silicon substrate to cause the formation of a dielectric layer which is generally parallel to the front surface of the substrate and is located in a region between the front surface and the central plane;

subjecting the silicon substrate to an ideal precipitating heat treatment to cause the formation of a non-uniform distribution of crystal lattice vacancies, with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer; and,

depositing an epitaxial layer on the front surface of the silicon substrate.

2. The process of claim 1 wherein the epitaxial layer is deposited on the front surface prior to subjecting the silicon substrate to the ideal precipitating heat-treatment.

3. The process of claim 2 wherein the oxygen is implanted into the silicon substrate prior to depositing the epitaxial layer.

4. The process of claim 2 wherein the oxygen is implanted into the silicon substrate after subjecting the silicon substrate to an ideal precipitating heat-treatment.

5. The process of claim 4 further comprising subjecting the silicon substrate to an oxygen precipitation and stabilization heat-treatment to cause the formation and stabilization of oxygen precipitates in the bulk layer and the formation of a precipitate-free zone in the surface layer.

6. The process of claim 5 wherein the oxygen precipitation and stabilization heat-treatment is performed after subjecting the silicon substrate to the ideal precipitating heat treatment and prior to implanting oxygen into the silicon substrate.

7. The process of claim 5 wherein the oxygen precipitation and stabilization heat-treatment causes the formation of secondary defects in the bulk layer.

8. The process of claim 2 wherein oxygen is implanted into the silicon substrate after depositing the epitaxial layer and prior to subjecting the silicon substrate to an ideal precipitating heat-treatment.

9. The process of claim 1 wherein the silicon substrate is subjected to the ideal precipitating heat-treatment prior to depositing the epitaxial layer on the surface of the silicon substrate.

10. The process of claim 9 further comprising subjecting the silicon substrate to an oxygen precipitation and stabilization heat-treatment to cause the formation and stabilization of oxygen precipitates in the bulk layer and the formation of a precipitate-free zone in the surface layer.

11. The process of claim 10 wherein the oxygen precipitation and stabilization heat-treatment is performed after subjecting the silicon substrate to the ideal precipitating heat-treatment and prior to depositing the epitaxial layer on the surface of the silicon substrate.

12. The process of claim 10 wherein the oxygen precipitation and stabilization heat-treatment causes the formation of secondary defects in the bulk layer.

13. The process of claim 9 wherein the oxygen is implanted into the silicon substrate prior to subjecting the silicon substrate to the ideal precipitating heat-treatment.

14. The process of claim 9 wherein the oxygen is implanted into the silicon substrate after depositing the epitaxial layer on the surface of the silicon substrate.

15. The process of claim 9 wherein the oxygen is implanted into the silicon substrate after subjecting the silicon substrate to the ideal precipitating heat treatment and before depositing the epitaxial layer on the surface of the silicon substrate.

16. The process of claim 15 further comprising subjecting the silicon substrate to an oxygen precipitation and stabilization heat-treatment to cause the formation and stabilization of oxygen precipitates in the bulk layer and the formation of a precipitate-free zone in the surface layer.

17. The process of claim 16 wherein the oxygen precipitation and stabilization heat-treatment is performed after subjecting the silicon substrate to the ideal precipitating heat-treatment and prior to implanting oxygen into the silicon substrate.

18. The process of claim 16 wherein the oxygen precipitation and stabilization heat-treatment causes the formation of secondary defects in the bulk layer.

19. The process of claim 1 wherein the silicon substrate comprises a first axially symmetric region in which there is a predominant intrinsic point defect and which is substantially free of agglomerated intrinsic point defects.

20. The process of claim 19 wherein silicon self-interstitials are the predominant intrinsic point defect within the first axially symmetric region, the first axially symmetric region extending radially inward from the circumferential edge of the silicon substrate and having a width, as measured from the circumferential edge radially toward the central axis, which is at least about 30% of the length of the radius of the silicon substrate.

21. The process of claim 20 wherein the first axially symmetric region is generally annular in shape and the silicon substrate additionally comprises a second axially symmetric region, that is generally cylindrical in shape, in which vacancies are the predominant intrinsic point defect, the second region located radially inward of the first region in the silicon substrate.

22. The process of claim 19 wherein silicon self-interstitials are the predominant intrinsic point defect within the first axially symmetric region, the first axially symmetric region extending radially inward from the circumferential edge of the silicon substrate and having a width, as measured from the circumferential edge radially toward the central axis, which is at least about 80% of the length of the radius of the silicon substrate.

23. The process of claim 22 wherein the first axially symmetric region is generally annular in shape and the silicon substrate additionally comprises a second axially symmetric region, that is generally cylindrical in shape, in which vacancies are the predominant intrinsic point defect, the second region located radially inward of the first region in the silicon substrate.

24. The process of claim 19 wherein silicon self-interstitials are the predominant intrinsic point defect within the first axially symmetric region, the first axially symmetric region extending radially inward from the circumferential edge of the silicon substrate and having a width, as measured from the circumferential edge radially toward the central axis, which is about equal to the length of the radius of the silicon substrate.

25. The process of claim 19 wherein vacancies are the predominant intrinsic point defect within the first axially symmetric region, the first axially symmetric region comprising the central axis of the silicon substrate or having a width of at least about 15 mm, as measured along the radius of the silicon substrate.

26. The process of claim 25 further comprising a second axially symmetric region, that is generally annular in shape, in which silicon self-interstitials are the predominant intrinsic point defect, the second region being located radially outward of the first region.

27. The process of claim 25 wherein the first axially symmetric region has a width which is at least about 25% of the length of the radius of the silicon substrate.

28. The process of claim 25 wherein the first axially symmetric region has a width which is about equal to the length of the radius of the silicon substrate.

29. A process for producing a silicon on insulator structure, the structure comprising a silicon substrate having two major, generally parallel surfaces, one of which is the front surface and the other of which is the back surface, a central plane between the front and back surfaces, a surface layer which comprises a first region of the substrate between the front surface and a distance, D 1 , of at least about 10 micrometers as measured from the front surface and toward the central plane, and a bulk layer which comprises a second region of the substrate between the central plane and the first region, a circumferential edge joining the front and back surfaces, a central axis, and a radius extending from the central axis to the circumferential edge, the process comprising:

implanting oxygen into the silicon substrate to cause the formation of a dielectric layer which is generally parallel to the front surface and is located in a region between the front surface and the central plane;

subjecting the silicon substrate to an ideal precipitating heat treatment to cause the formation of a non-uniform distribution of crystal lattice vacancies, with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer; and,

subjecting said heat treated substrate to an oxygen precipitation and stabilization heat-treatment to cause to formation and stabilization of oxygen precipitates in the bulk layer and a precipitate-free zone in the surface layer.

30. The process of claim 29 wherein oxygen is implanted into the silicon substrate after subjecting the heat treated silicon substrate to the oxygen precipitation and stabilization heat-treatment.

31. The process of claim 29 wherein the oxygen precipitation and stabilization heat-treatment causes the formation of secondary defects in the bulk layer.

32. The process of claim 29 wherein oxygen is implanted into the silicon substrate prior to subjecting the silicon substrate to the ideal precipitating heat treatment.

33. The process of claim 29 wherein the silicon substrate comprises a first axially symmetric region in which there is a predominant intrinsic point defect and which is substantially free of agglomerated intrinsic point defects.

34. The process of claim 33 wherein silicon self-interstitials are the predominant intrinsic point defect within the first axially symmetric region, the first axially symmetric region extending radially inward from the circumferential edge of the silicon substrate and having a width, as measured from the circumferential edge radially toward the central axis, which is at least about 30% of the length of the radius of the silicon substrate.

35. The process of claim 34 wherein the first axially symmetric region is generally annular in shape and the silicon substrate additionally comprises a second axially symmetric region, that is generally cylindrical in shape, in which vacancies are the predominant intrinsic point defect, the second region located radially inward of the first region in the silicon substrate.

36. The process of claim 33 wherein silicon self-interstitials are the predominant intrinsic point defect within the first axially symmetric region, the first axially symmetric region extending radially inward from the circumferential edge of the silicon substrate and having a width, as measured from the circumferential edge radially toward the central axis, which is at least about 80% of the length of the radius of the silicon substrate.

37. The process of claim 36 wherein the first axially symmetric region is generally annular in shape and the silicon substrate additionally comprises a second axially symmetric region, that is generally cylindrical in shape, in which vacancies are the predominant intrinsic point defect, the second region located radially inward of the first region in the silicon substrate.

38. The process of claim 33 wherein silicon self-interstitials are the predominant intrinsic point defect within the first axially symmetric region, the first axially symmetric region extending radially inward from the circumferential edge of the silicon substrate and having a width, as measured from the circumferential edge radially toward the central axis, which is about equal to the length of the radius of the silicon substrate.

39. The process of claim 33 wherein vacancies are the predominant intrinsic point defect within the first axially symmetric region, the first axially symmetric region comprising the central axis of the silicon substrate or having a width of at least about 15 mm, as measured along the radius of the silicon substrate.

40. The process of claim 39 further comprising a second axially symmetric region, that is generally annular in shape, in which silicon self-interstitials are the predominant intrinsic point defect, the second region being located radially outward of the first region.

41. The process of claim 39 wherein the first axially symmetric region has a width which is at least about 25% of the length of the radius of the silicon substrate.

42. The process of claim 39 wherein the first axially symmetric region has a width which is about equal to the length of the radius of the silicon substrate.

Assignments (8)
NOTICE OF LICENSE AGREEMENT Recorded Jun 6, 2014
From: SUNEDISON SEMICONDUCTOR LIMITED
To: SUNEDISON SEMICONDUCTOR TECHNOLOGY PTE. LTD.
Reel/Frame 033099/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: MEMC ELECTRONIC MATERIALS, INC.
To: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)
Reel/Frame 033023/0430 →
RELEASE OF SECURITY INTEREST Recorded Mar 3, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC.
Reel/Frame 032382/0724 →
SECURITY AGREEMENT Recorded Jan 30, 2014
From: SUNEDISON, INC.; SOLAICX; SUN EDISON, LLC; NVT, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 032177/0359 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: BANK OF AMERICA, N.A.
To: ENFLEX CORPORATION; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0031 →
RELEASE OF SECURITY INTEREST Recorded Dec 26, 2013
From: GOLDMAN SACHS BANK USA
To: NVT, LLC; SUN EDISON LLC; SOLAICX; SUNEDISON, INC. (F/K/A MEMC ELECTRONIC MATERIALS, INC.)
Reel/Frame 031870/0092 →
SECURITY AGREEMENT Recorded Oct 1, 2012
From: NVT, LLC; SUN EDISON LLC; SOLAICX, INC.; MEMC ELECTRONIC MATERIALS, INC.
To: GOLDMAN SACHS BANK USA
Reel/Frame 029057/0810 →
SECURITY AGREEMENT Recorded Apr 1, 2011
From: MEMC ELECTRONIC MATERIALS, INC.; SUNEDISON LLC; SOLAICX
To: BANK OF AMERICA, N.A.
Reel/Frame 026064/0720 →