Granted Patent B2

US 7,371,665 · App. 11/176,083 · Granted May 13, 2008

Abstract

Claims (33)

1. A method for fabricating an isolation layer of a semiconductor device comprising:

forming a sacrificial layer on a substrate;

forming a moat pattern which defines an active area and an isolation area by coating a photoresist on the sacrificial layer and performing an exposure and development process to the coated photoresist;

patterning the sacrificial layer by using the moat pattern as a mask;

forming an insulating layer on an entire surface of the substrate including the patterned sacrificial layer after removing the moat pattern;

forming spacers at the sidewalls of the patterned sacrificial layer by anisotropically etching the insulating layer;

removing the patterned sacrificial layer and exposing an entire surface of the substrate except for areas of the substrate under the spacers;

depositing a silicon layer on an entire surface of the substrate including the spacers, wherein the silicon layer is deposited on both an inside and an outside of each of the spacers at the same time; and

planarizing the surface of the silicon layer and the spacers by CMP.

2. The method of claim 1 , wherein the sacrificial layer comprises polysilicon.

3. The method of claim 1 , wherein the sacrificial layer comprises an insulating material having a greater etching select ratio than the insulating layer.

4. The method of claim 1 , wherein the insulating layer comprises an STI layer.

5. The method of claim 1 , wherein the sacrificial layer has a thickness of 1000-2000 Å.

6. The method of claim 1 , wherein the insulating layer comprises a nitride layer.

7. The method of claim 1 , wherein the sacrificial layer comprises an oxide layer.

8. The method of claim 1 , wherein patterning the sacrificial layer comprises a dry etch process.

9. The method of claim 1 , wherein depositing the silicon layer comprises epitaxial growth.

10. A method for fabricating an isolation layer of a semiconductor device comprising:

forming a sacrificial layer comprising an insulating material on a substrate;

patterning the sacrificial layer to define an active area and an isolation area;

forming an insulating layer with a lesser etching select ratio than the insulating material on an entire surface of the substrate including the patterned sacrificial layer;

forming spacers at the sidewalls of the patterned sacrificial layer by anisotropically etching the insulating layer;

removing the patterned sacrificial layer and exposing an entire surface of the substrate except for areas of the substrate under the spacers;

epitaxially growing a silicon layer on the substrate in contact with the spacers, wherein the silicon layer is epitaxially grown on both an inside and an outside of each of the spacers at the same time; and

planarizing the silicon layer and the spacers by CMP.

11. The method of claim 10 , wherein the sacrificial layer comprises polysilicon.

12. The method of claim 10 , wherein planarizing the silicon layer and the spacers forms a coplanar upper surface on the silicon layer and the spacers.

13. The method of claim 10 , wherein the sacrificial layer is deposited to a thickness of 1000-2000 Å.

14. The method of claim 10 , wherein the insulating layer comprises a nitride layer.

15. The method of claim 10 , wherein the sacrificial layer comprises an oxide layer.

16. The method of claim 10 , further comprising forming a moat pattern by coating a photoresist on the sacrificial layer and performing an exposure and development process on the coated photoresist before patterning the sacrificial layer.

17. The method of claim 16 , wherein patterning the sacrificial layer comprises a dry etch process.

18. The method of claim 1 , wherein the distance between the spacers defines a critical dimension of a Shallow Trench Isolation structure.

Assignments (9)