Method for fabricating metal line in a semiconductor
View Patent ↗A metal line is fabricated in a semiconductor device by a method including: forming an etch stop layer on a substrate; forming an interlayer insulating layer on the etch stop layer, the interlayer insulating layer including dual damascene patterns, each respectively having a trench and a via contact hole; forming a barrier metal layer and a line metal layer on the interlayer insulating layer and in the dual damascene patterns; forming an anti-oxidation layer on above the line metal layer; and forming a metal line in the dual damascene patterns by planarizing an entire surface of the anti-oxidation layer.
1. A method for fabricating a metal line in a semiconductor device, comprising:
forming an etch stop layer on a substrate;
forming an interlayer insulating layer on the etch stop layer, the interlayer insulating layer comprising a plurality of dual damascene patterns, each respectively having a trench and at least one via contact hole;
forming a barrier metal layer and a line metal layer on the interlayer insulating layer including in the dual damascene patterns;
performing an edge bead removal (EBR) process;
forming an anti-oxidation layer above the line metal layer;
cleaning the semiconductor device; and
forming a metal line in the dual damascene pattern by planarizing an entire surface of the anti-oxidation layer and exposing a surface of the interlayer insulating layer.
2. The method of claim 1 , the barrier metal layer comprises a metal/metal nitride bilayer.
3. The method of claim 1 , comprising performing the edge bead removal (EBR) process during or after the step of forming the line metal layer, then cleaning the semiconductor device before the step of forming the anti-oxidation layer.
4. The method of claim 1 , comprising performing the edge bead removal (EBR) process during or after the step of forming the line metal layer, then cleaning the semiconductor device after the step of forming the anti-oxidation layer.
5. The method of claim 1 , wherein forming the line metal layer comprises depositing and then annealing the line metal layer.
6. The method of claim 2 , wherein forming the line metal layer comprises depositing and then annealing the line metal layer.
7. The method of claim 3 , wherein forming the line metal layer comprises depositing and then annealing the line metal layer.
8. The method of claim 4 , wherein forming the line metal layer comprises depositing and then annealing the line metal layer.
9. The method of claim 1 , wherein depositing the anti-oxidation layer comprises spin coating, CVD, spraying, or dipping.
10. The method of claim 2 , wherein depositing the anti-oxidation layer comprises spin coating, CVD, spraying, or dipping.
11. The method of claim 3 , wherein depositing the anti-oxidation layer comprises spin coating, CVD, spraying, or dipping.
12. The method of claim 4 , wherein depositing the anti-oxidation layer comprises spin coating, CVD, spraying, or dipping.
13. The method of claim 5 , wherein depositing the anti-oxidation layer comprises spin coating, CVD, spraying, or dipping.
14. The method of claim 6 , wherein depositing the anti-oxidation layer comprises spin coating, CVD, spraying, or dipping.
15. The method of claim 7 , wherein depositing the anti-oxidation layer comprises spin coating, CVD, spraying, or dipping.
16. The method of claim 8 , wherein depositing the anti-oxidation layer comprises spin coating, CVD, spraying, or dipping.
17. The method of claim 1 , wherein the step of planarizing the entire surface of the anti-oxidation layer comprises polishing the anti-oxidation layer, the line metal layer and the barrier metal layer.
18. The method of claim 1 , wherein the barrier metal layer comprises a TiN/Ti layer or a TaN/Ta layer.
19. The method of claim 1 , wherein the anti-oxidation layer comprises a member selected from the group consisting of polymeric films, dielectric films, gold coatings and chromate films.
20. The method of claim 1 , wherein the line metal layer comprises a Cu layer.