Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor
View Patent ↗The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.
1. A method for forming an integrated circuit comprising:
providing a substrate prepared with isolation regions and a gate of a transistor on a device region within the isolation regions;
recessing the substrate in regions adjacent to the gate and isolation regions to create recesses;
forming stressors in the recesses, the stressors induce a stress in a channel region beneath the gate, wherein a stressor comprises a top surface having a horizontal portion and a sloping portion relative to a top surface of the substrate, with the horizontal portion located adjacent to the gate and the sloping portion located adjacent to the isolation region; and
forming dielectric stressor spacers on the sloping portions of the stressors, wherein the dielectric stressor spacers reduce silicide strapping of the source and drain to body.
2. The method of claim 1 wherein the stressors comprises silicon formed by epitaxial growth, including SiGe, SiC and SiBGe.
3. The method of claim 1 wherein forming the stressors results in forming pits between the sloping portions of the stressors and isolation regions.
4. The method of claim 3 wherein the stressors comprises silicon formed by epitaxial growth, including SiGe, SiC and SiBGe.
5. The method of claim 1 further comprises:
forming source and drain of the transistor in the stressors; and
forming silicide contacts on surfaces of the stressors unprotected by the dielectric stressor spacers.
6. The method of claim 5 wherein the stressors comprises silicon formed by epitaxial growth, including SiGe, SiC and SiBGe.
7. The method of claim 5 wherein forming the stressors results in forming pits between the sloping portions of the stressors and isolation regions.
8. The method of claim 7 wherein the stressors comprises silicon formed by epitaxial growth, including SiGe, SiC and SiBGe.
9. The method of claim 1 wherein:
the gate includes L-shaped gate sidewall spacers and sacrificial spacers over the gate sidewall spacers; and
forming dielectric stressor spacers comprises
removing the sacrificial spacers,
depositing a dielectric layer on the substrate, and
anisotropically etching the dielectric layer to form the dielectric stressor spacers.
10. The method of claim 9 further comprises:
forming source and drain of the transistor in the stressors; and
forming silicide contacts on surfaces of the stressors unprotected by dielectric stressor spacers.
11. The method of claim 10 wherein the stressors comprises silicon formed by epitaxial growth, including SiGe, SiC and SiBGe.
12. The method of claim 10 wherein forming the stressors results in forming pits between the sloping portions of the stressors and isolation regions.
13. The method of claim 12 wherein the stressors comprises silicon formed by epitaxial growth, including SiGe, SiC and SiBGe.
14. A method for forming a semiconductor device comprising:
providing a substrate prepared with an isolation region adjacent to a device region with a device feature thereon;
forming a recess in the device region between the isolation region and device feature;
forming a stressor in the recess, the stressor induces a stress in the substrate under the device feature, wherein the stressor comprises a top surface having a horizontal portion and a sloping portion relative to a top surface of the substrate, the horizontal surface is located adjacent to the device feature and the sloping portion is located adjacent to the isolation region; and
forming a dielectric stressor spacer on the sloping portion of the stressor.
15. The method of claim 14 wherein forming the stressor results in forming a pit between the sloping portion of the stressor and isolation region.
16. The method of claim 15 wherein the stressor comprises silicon formed by epitaxial growth, including SiGe, SiC and SiBGe.
17. The method of claim 14 wherein the device feature comprises a gate of a transistor and further comprises:
forming first and second recesses adjacent to the gate and the isolation region; and
forming first and second stressors in the first and second recesses;
forming first and second dielectric stressor spacers on the sloping portions of the first and second stressors; and
forming source and drain of the transistor in the stressors.
18. The method of claim 17 wherein the gate includes L-shaped gate sidewall spacers and sacrificial spacers over the gate sidewall spacers, and:
wherein forming the dielectric stressor spacers comprises
removing the sacrificial spacers,
depositing a dielectric layer on the substrate, and
anisotropically etching the dielectric layer to form the dielectric stressor spacers; and
further comprises forming silicide contacts on surfaces of stressors unprotected by the dielectric stressor spacers.
19. The method of claim 17 wherein forming the stressors results in forming pits between the sloping portions of the stressors and isolation regions.
20. The method of claim 19 wherein the gate includes L-shaped gate sidewall spacers and sacrificial spacers over the gate sidewall spacers, and:
wherein forming the dielectric stressor spacers comprises
removing the sacrificial spacers,
depositing a dielectric layer on the substrate, and
anisotropically etching the dielectric layer to form the stressor spacers; and
further comprises forming silicide contacts on surfaces of stressors unprotected by the dielectric stressor spacers.
21. A method of forming a transistor comprising:
providing a substrate with a device region defined thereon, wherein the substrate is prepared with isolation regions surrounding the device region and a gate on the device region;
etching the substrate to form first and second recesses in the substrate adjacent to the gate and isolation regions;
forming stressors in the recesses, wherein a stressor comprises a top surface having horizontal and sloping surface portions, the horizontal surface portion is located adjacent to the gate and the sloping surface portion is located adjacent to the isolation region; and
forming dielectric stressor spacers on the sloping surface portions of the stressors.
22. The method of claim 21 wherein:
the gate includes L-shaped gate sidewall spacers and sacrificial spacers over the gate sidewall spacers; and
forming the dielectric stressor spacers comprises
removing the sacrificial spacers,
depositing a dielectric layer on the substrate, and
anisotropically etching the dielectric layer to form the dielectric stressor spacers.
23. The method of claim 22 further comprises:
forming source and drain of the transistor in the stressors; and
forming silicide contacts on surfaces of the stressors unprotected by the dielectric stressor spacers.
24. The method of claim 21 wherein forming the stressors results in forming a pit between the sloping surface portions of the stressors and isolation regions.
25. The method of claim 24 wherein:
the gate includes L-shaped gate sidewall spacers and sacrificial spacers over the gate sidewall spacers; and
forming the dielectric stressor spacers comprises
removing the sacrificial spacers,
depositing a dielectric layer on the substrate, and
anisotropically etching the dielectric layer to form the dielectric stressor spacers.
26. The method of claim 25 further comprises:
forming source and drain of the transistor in the stressors; and
forming silicide contacts on surfaces of stressors unprotected by dielectric stressor spacers.