Method for forming high reliability bump structure
View Patent ↗Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask. Thereafter, the electrically conductive material is reflowed to provide a bump on the semiconductor substrate.
1. A method for forming a bump on a semiconductor device, comprising:
forming a first passivation layer on the semiconductor device;
patterning and etching the first passivation layer to form a plurality of openings in the first passivation layer;
forming a contact pad layer over the etched first passivation layer;
patterning and etching the contact pad layer to form a contact pad, the contact pad having a plurality of openings therein;
forming a second passivation layer over the first passivation layer and the contact pad;
patterning and etching the second passivation layer to form an opening in the second passivation layer partially exposing a surface of the contact pad; and
depositing a UBM (Under Bump Metallurgy) layer over the etched second passivation layer and the contact pad, and in the plurality of openings of the contact pad.
2. The method of claim 1 , further comprising:
forming a photoresist layer on the UBM layer; and
patterning and etching the photoresist layer to form at least one opening substantially overlying the contact pad.
3. The method of claim 2 , further comprising:
depositing an electrically conductive material into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad;
removing the remaining portion of the photoresist layer;
etching the UBM layer using the electrically conductive material as a mask; and
reflowing the electrically conductive material to provide a bump on the semiconductor device.
4. The method of claim 1 , wherein the UBM layer comprises:
one or more layers of different metallic composition.
5. The method of claim 1 , wherein the UBM layer comprises:
an adhesion layer;
a wetting layer formed above the adhesion layer; and
a protection layer formed above the wetting layer.
6. A method for forming a bump on a semiconductor device having a top metal layer therein, the method comprising:
forming a first passivation layer on the semiconductor device;
patterning and etching the first passivation layer to form a plurality of openings in the first passivation layer exposing portions of the top metal layer;
forming a contact pad layer over the etched first passivation layer, the contact pad layer being in contact with the top metal layer;
patterning and etching the contact pad layer to form a contact pad substantially overlying the top metal layer, the contact pad having a plurality of openings therein;
forming a second passivation layer over the first passivation layer and the contact pad;
patterning and etching the second passivation layer to form an opening in the second passivation layer partially exposing a surface of the contact pad; and
depositing a UBM (Under Bump Metallurgy) layer over the etched second passivation layer and the contact pad, and in the plurality of openings of the contact pad.
7. The method of claim 6 , further comprising:
forming a photoresist layer on the UBM layer; and
patterning and etching the photoresist layer to form at least one opening substantially overlying the contact pad.
8. The method of claim 7 , further comprising:
depositing an electrically conductive material into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad;
removing the remaining portion of the photoresist layer;
etching the UBM layer using the electrically conductive material as a mask; and
reflowing the electrically conductive material to provide a bump on the semiconductor device.
9. The method of claim 6 , wherein the UBM layer comprises:
an adhesion layer;
a wetting layer formed above the adhesion layer; and
a protection layer formed above the wetting layer.
10. A bump structure on a semiconductor substrate, comprising:
a semiconductor substrate having a top metal layer formed therein;
a patterned and etched first passivation layer formed on the substrate, the first passivation layer having a plurality of openings exposing portions of the top metal layer;
a contact pad formed over the plurality of openings of the first passivation layer, the contact pad having a plurality of openings therein;
a patterned and etched second passivation layer formed over the first passivation layer and the contact pad, the second passivation layer having an opening therein exposing a surface of the contact pad; and
a patterned and etched UBM (Under Bump Metallurgy) layer formed over portions of the etched second passivation layer and the contact pad, and in the plurality of openings of the contact pad.
11. The bump structure of claim 10 , further comprising:
a bump formed on the etched UBM layer.
12. The bump structure of claim 10 , wherein the UBM layer comprises:
an adhesion layer;
a wetting layer formed above the adhesion layer; and
a protection layer formed above the wetting layer.