Electronic device including discontinuous storage elements
View Patent ↗An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
1. An electronic device comprising:
a substrate including a first trench that includes a first wall, a second wall, and a bottom lying between the first and second walls, wherein the first wall and the second wall extend from a primary surface of the substrate;
a first dielectric layer lying along the first and second walls of the first trench;
discontinuous storage elements, wherein:
a first portion of the discontinuous storage elements lies at least within the first trench; and
the first dielectric layer lies between the first portion of the discontinuous storage elements and the first and second walls of the first trench;
a second dielectric layer;
a first gate electrode, wherein at least a part of the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench, wherein:
the second dielectric layer lies between the first portion of the discontinuous storage elements and the first gate electrode;
the first gate electrode includes a first surface and a second surface, wherein the first surface is farthest from the bottom of the first trench, and the second surface is opposite the first surface; and
the second surface of the first gate electrode overlies a plurality of discontinuous storage elements within the first portion of the storage elements along the bottom of the first trench; and
a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
2. The electronic device of claim 1 , wherein the first surface of the first gate electrode lies below the primary surface of the substrate.
3. The electronic device of claim 2 , wherein the second gate electrode extends at least partly into the first trench.
4. The electronic device of claim 2 , further comprising a third gate electrode, wherein:
the substrate further includes a second trench that is spaced apart from the first trench, wherein the second trench includes a wall and a bottom and extends from the primary surface of the substrate;
a third dielectric layer lying along the wall and bottom of the second trench;
a second portion of the discontinuous storage elements lies at least within the second trench, wherein the third dielectric layer lies between the second portion of the discontinuous storage elements and the wails of the second trench;
a fourth dielectric layer; and
the third gate electrode has an upper surface that lies below the primary surface of the substrate, wherein the fourth dielectric layer lies between the second portion of the discontinuous storage elements and the third gate electrode, and at least a part of the second portion of the discontinuous storage elements lies between the third gate electrode and the wall of the second trench.
5. The electronic device of claim 4 , further comprising:
a first doped region lying within the substrate below the first trench; and
a second doped region lying within the substrate below the second trench.
6. The electronic device of claim 5 , further comprising a third doped region lying along the primary surface of the substrate between the first and second trenches.
7. The electronic device of claim 6 , wherein the third doped region extends to the walls of the first and second trenches.
8. The electronic device of claim 6 , wherein the third doped region is spaced apart from the walls of the first and second trenches.
9. The electronic device of claim 5 , further comprising:
a first charge storage region that includes a first discontinuous storage element within the first portion of the discontinuous storage elements, wherein the first discontinuous storage element lies closer to the upper surface of the first gate electrode than the first doped region; and
a second charge storage region that includes a second discontinuous storage element within the second portion of the discontinuous storage elements, wherein the second discontinuous storage element lies closer to the upper surface of the third gate electrode than the second doped region, and wherein the second charge storage region is spaced apart from the first charge storage region.
10. The electronic device of claim 4 , wherein the second gate electrode overlies the first gate electrode, the third gate electrode, and a portion of the substrate between the first and second trenches.
11. The electronic device of claim 4 , further comprising a fourth gate electrode, wherein:
the second gate electrode overlies the first gate electrode and a first portion of the substrate between the first and second trenches; and
the fourth gate electrode overlies the third gate electrode and a second portion of the substrate between the first and second trenches.
12. The electronic device of claim 1 , further comprising a third gate electrode overlying the first gate electrode and the primary surface of the substrate, wherein:
the first, second and third gate electrodes have lengths substantially parallel to one another;
a first memory cell includes a first plurality of the discontinuous storage elements within the first portion of the discontinuous storage elements, the first gate electrode, and the second gate electrode; and
a second memory cell includes a second plurality of the discontinuous storage elements within the first portion of the discontinuous storage elements, the first gate electrode, and the third gate electrode.
13. The electronic device of claim 1 , wherein the discontinuous storage elements comprise silicon nanocrystals or metal nanoclusters.
14. The electronic device of claim 1 , further comprising an array, wherein:
the substrate includes a plurality of trenches, including the first trench; and
within the array, the discontinuous storage elements lie only within the trenches of the substrate.
15. The electronic device of claim 14 , further comprising a third dielectric layer overlying the first gate electrode and comprising an upper surface within the first trench, wherein:
the first portion of the discontinuous storage elements is spaced apart from the primary surface of the substrate; and
substantially none of the discontinuous storage elements within the first portion of the discontinuous storage elements lie at an elevation higher than a lowermost elevation of the upper surface of the third dielectric layer.
16. The electronic device of claim 1 , wherein from a cross-sectional view, the first gate electrode has a substantially rectangular shape.
17. The electronic device of claim 1 , wherein from a cross-sectional view:
the first gate electrode includes portions; and
the portions of the first gate electrode include curved outer surfaces that face each other.
18. An electronic device comprising:
a substrate including a first trench and a second trench that are spaced apart from each other, wherein each of the first and second trenches includes a first wall, a second wall and a bottom lying between the first and second walls, and wherein the first and second walls extend from a primary surface of the substrate;
a first dielectric layer lying along the first and second walls of the first and second trenches;
discontinuous storage elements, wherein a first portion of the discontinuous storage elements lies within the first trench, and a second portion of the discontinuous storage elements lies at least within the second trench;
a second dielectric layer;
a first gate electrode lying within the first trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a pail of the first portion of the discontinuous storage elements lies between the first gate electrode and the first and second walls of the first trench, and wherein the second dielectric layer lies between the first portion of the discontinuous storage elements and the first gate electrode;
a second gate electrode lying within the second trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the second portion of the discontinuous storage elements lies between the second gate electrode and the wall of the second trench, and when the second dielectric layer lies between the second portion of the discontinuous storage elements and the second gate electrode;
a third gate electrode overlying the first gate electrode, the second gate electrode, and the primary surface of the substrate between the first and second trenches; and
a fourth gate electrode spaced apart from the third gate electrode and overlying the first gate electrode, the second gate electrode, and the primary surface of the substrate between the first and second trenches,
wherein:
a first memory cell within the electronic device comprises a first plurality of the discontinuous storage elements within the first portion of the discontinuous storage elements, the first gate electrode, and the third gate electrode;
a second memory cell within the electronic device comprises a second plurality of the discontinuous storage elements within the first portion of the discontinuous storage elements, the first gate electrode, and the fourth gate electrode;
the first and second memory cells are spaced apart from each other without another memory cell lying between the first and second memory cells;
a third plurality of the discontinuous storage elements within the first portion of the discontinuous storage elements lie along the first and second walls and the bottom of the first trench between the third and fourth gate electrodes, wherein the third plurality of discontinuous storage elements are separate from the first and second memory cells;
a third memory cell within the electronic device comprises a fourth plurality of the discontinuous storage elements within the second portion of the discontinuous storage elements, the second gate electrode, and the third gate electrode;
a fourth memory cell within the electronic device comprises a fifth plurality of the discontinuous storage elements within the second portion of the discontinuous storage elements, the second gate electrode, and the fourth gate electrode; and
the third and fourth memory cells are spaced apart from each other without another memory cell lying between the third and fourth memory cells; and
a sixth plurality of the discontinuous storage elements within the second portion of the discontinuous storage elements lie alone the first and second walls and the bottom of the second trench between the third and fourth gate electrodes, wherein the sixth plurality of discontinuous storage elements are separate from the third and fourth memory cells.
19. The electronic device of claim 18 , further comprising:
a first doped region lying within the substrate along the bottom of the first trench;
a second doped region lying within the substrate along the bottom of the second trench; and
a third doped region lying along the primary surface of the substrate between the first and second trenches.
20. A memory cell comprising:
a substrate including a first trench and a second trench that are spaced apart from each other, wherein each of the first and second trenches includes a wall and a bottom and extends from a primary surface of the substrate;
a first doped region lying within the substrate along the bottom of the first trench;
a second doped region lying within the substrate along the bottom of the second trench;
a first dielectric layer lying along the walls and bottoms of the first and second trenches;
discontinuous storage elements, wherein:
a first portion of the discontinuous storage elements lies within the first trench;
a second portion of the discontinuous storage elements lies within the second trench;
the first and second portions of the discontinuous storage elements are spaced apart from each other and the primary surface of the substrate; and
substantially none of the discontinuous storage elements overlie the primary surface of the substrate between the first and second trenches;
a second dielectric layer adjacent to the discontinuous storage elements within the first and second trenches;
a first gate electrode lying within the first trench and having an upper surface that lies below the primary surface of the substrate, wherein:
a first plurality of the discontinuous storage elements within the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench;
the first plurality of the discontinuous storace elements includes a first charge storage region of the memory cell; and
a first part of the second dielectric layer lies between the fist plurality of the discontinuous storage elements and the first gate electrode;
a second gate electrode lying within the second trench and having an upper surface that lies below the primary surface of the substrate, wherein:
a second plurality of the discontinuous storage elements within the second portion of the discontinuous storage elements lies between the second gate electrode and the wall of the second trench;
the second plurality of the discontinuous storage elements includes a second charge storage region of the memory cell; and
a second part of the second dielectric layer lies between the second plurality of the discontinuous storage elements and the second gate electrode;
a third dielectric layer including a first portion overlying the first gate electrode within the first trench and a second portion overlying the second gate electrode within the second trench; and
a third gate electrode overlying the third dielectric layer and at least one of the first gate electrode or the second gate electrode, wherein the third gate electrode lies at least partly within the first trench and the second trench.