Method of controlling mode register set operation in memory device and circuit thereof
View Patent ↗Disclosed is a method of controlling an MRS operation in a memory device which can prevent an unnecessary MRS operation due to a malfunction of the memory device at a time when the memory device exits from a self-refresh mode. According to this method, external addresses are used to intercept a mode register set command signal that enables the MRS operation at a time point at which the memory device exits from the self-refresh mode.
1. A method of controlling a mode register set (MRS) operation in a memory device when the memory device exits from a self-refresh mode, the method comprising the step of:
intercepting a mode register set command signal that enables the MRS operation using an external address applied to an address decoding circuit through a plurality of address pins for deciding a burst length and a column address strobe (CAS) latency, said mode register set command signal enabling the MRS operation, after the memory device exits a self-refresh mode; and
simultaneously with the interception of the mode register set command signal, receiving a plurality of address signals of the memory device and disabling the transmission of the mode register set command signal to a memory device through a transmission gate, when the plurality of address signals are logic zero.
2. The method as claimed in claim 1 , wherein the external address applied to the address pins is in a logic low state.
3. The method as claimed in claim 1 , wherein the mode register set command signal is enabled when signals of /CS (Chip Select), /RAS (Row Address Strobe), /CAS (Column Address Strobe) and /WE (Write Enable) are all in a logic low state.
4. The method as claimed in claim 1 , wherein the signals of /CS, /RAS, /CAS and /WE are all in a logic low state at the time when the memory device exits from the self-refresh mode.
5. A circuit for controlling a mode register set (MRS) operation in a memory device that receives an MRS-related control signal and outputting a mode register set command signal for enabling the MRS operation, the circuit comprising:
an input driver circuit that receives an external address, a mode decision address and the mode register set command signal the, the input driver circuit having an output, coupled to an input of a switching circuit, the switching circuit having an output and having a control input, the signal input to the control input of the switching circuit selectably enabling and disabling transmission of the signal output from the input driver circuit to a memory device from the switching circuit output; and
a control circuit that receives a plurality of address signals from a plurality of address lines, the control circuit having an output coupled to the control input of the switching circuit such that the switching circuit will block transmission of the mode register set command signal from the input driver circuit when the plurality of address lines input to said control circuit are logic zero.
6. The circuit as claimed in claim 5 , wherein if the switching circuit is enabled, the mode register set command signal is intercepted.
7. The circuit as claimed in claim 5 , wherein when the address lines input to the control circuit are at a logic zero state, the switching circuit is enabled.
8. The circuit as claimed in claim 5 , wherein the external address is applied through a plurality of address pins for deciding a burst length and a column address strobe (CAS) latency.