Efficient switching architecture with reduced stub lengths
View Patent ↗A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.
1. A switching topology for automatic test equipment, comprising:
a plurality of switching circuits for conveying, without interruption, propagating signals to alternative signal paths, each of the plurality of switching circuits having first through fourth nodes, wherein the first and second nodes are connectable to the third and fourth nodes, respectively, to form a THROUGH connection, or to the fourth and third nodes, respectively, to form a CROSSED connection,
wherein each of the plurality of switching circuits includes first and second switching elements each having a common point and first and second connection points to which the common point is selectively connectable, wherein the common point of the first switching element is coupled to the first node, the common point of the second switching element is coupled to the second node, the first connection points of the first and second switching elements are coupled together at the third node, and the second connection points of the first and second switching elements are coupled together at the fourth node,
wherein each of the first through fourth nodes of any of the plurality of switching circuits is connected to at most one of the first through fourth nodes of all the others of the plurality of switching circuits,
wherein the plurality of switching circuits is arranged in the form of at least first through third N-by-N switching units each comprising at least one of the plurality of switching circuits,
wherein N/2 nodes of the first N-by-N switching unit are coupled to N/2 nodes of the third N-by-N switching unit, and
wherein N/2 nodes of the second N-by-N switching unit are coupled to N/2 nodes of the third N-by-N switching unit.
2. A switching topology as recited in claim 1 , further comprising a fourth N-by-N switching unit,
wherein N/2 nodes of the first N-by-N switching unit are coupled to N/2 nodes of the fourth N-by-N switching unit; and
wherein N/2 nodes of the second N-by-N switching unit are coupled to N/2 nodes of the fourth N-by-N switching unit.
3. A switching topology as recited in claim 2 , wherein N equals 2.
4. A switching topology as recited in claim 2 , further comprising fifth and sixth N-by-N switching units,
wherein N/2 nodes of the third N-by-N switching unit are coupled to N/2 nodes of the fifth N-by-N switching unit;
wherein N/2 nodes of the third N-by-N switching unit are coupled to N/2 nodes of the sixth N-by-N switching unit;
wherein N/2 nodes of the fourth N-by-N switching unit are coupled to N/2 nodes of the fifth N-by-N switching unit; and
wherein N/2 nodes of the fourth N-by-N switching unit are coupled to N/2 nodes of the sixth N-by-N switching unit.
5. A switching topology as recited in claim 4 , wherein N equals 2.
6. A switching topology as recited in claim 1 , further comprising fourth and fifth N-by-N switching units,
wherein N/2 nodes of the third N-by-N switching unit are coupled to N/2 nodes of the fourth N-by-N switching unit;
wherein N/2 nodes of the third N-by-N switching unit are coupled to N/2 nodes of the fifth N-by-N switching unit;
wherein N/2 nodes of the first N-by-N switching unit are coupled to N/2 nodes of the fourth N-by-N switching unit; and
wherein N/2 nodes of the second N-by-N switching unit are coupled to N/2 nodes of the fifth N-by-N switching unit.
7. A switching topology as recited in claim 6 , wherein N equals 2.
8. The switching topology as recited in claim 1 , wherein, for each of the plurality of switching circuits, the first and second switching elements are devices coupled to a circuit substrate, and wherein the first connection points of the first and second switching elements are coupled together via a conductive pathway on the circuit substrate.
9. The switching topology as recited in claim 8 , wherein the conductive pathway on the circuit substrate is substantially as short as possible.
10. The switching topology as recited in claim 8 , wherein, for each of the plurality of switching circuits, the second connection points of the first and second switching elements are coupled together via another conductive pathway on the circuit substrate.
11. The switching topology as recited in claim 10 , wherein the other conductive pathway on the circuit substrate is substantially as short as possible.
12. The switching topology as recited in claim 10 , wherein, for each of the plurality of switching circuits, the first and second switching elements are disposed within a single device package with conductive leads extending from the device package to the circuit substrate.
13. The switching topology as recited in claim 10 , wherein the circuit substrate is a printed circuit board.
14. A switching topology for automatic test equipment, comprising:
a plurality of switching circuits for conveying, without interruption, propagating signals to alternative signal paths, each of the plurality of switching circuits having first through fourth nodes, wherein the first and second nodes are connectable to the third and fourth nodes, respectively, to form a THROUGH connection, or to the fourth and third nodes, respectively, to form a CROSSED connection,
wherein each of the plurality of switching circuits includes
a first switching element having a common point and first and second connection points to which the common point is selectively connectable, the common point coupled to the first node and the first and second connection points each coupled to one of the third and fourth nodes, and
a second switching element having a common point and first and second connection points to which the common point is selectively connectable, the common point coupled to the second node and the first and second connection points each coupled to one of the third and fourth nodes,
wherein each of the first through fourth nodes of any of the plurality of switching circuits is connected to at most one of the first through fourth nodes of all the others of the plurality of switching circuits,
wherein the plurality of switching circuits is arranged in the form of at least first through fourth N-by-N switching units each comprising at least one of the plurality of switching circuits,
wherein N/2 nodes of the first N-by-N switching unit are coupled to N/2 nodes of the third N-by-N switching unit,
wherein N/2 nodes of the second N-by-N switching unit are coupled to N/2 nodes of the fourth N-by-N switching unit,
wherein N/2 nodes of the first N-by-N switching unit are coupled to N/2 nodes of the fourth N-by-N switching unit, and
wherein N/2 nodes of the second N-by-N switching unit are coupled to N/2 nodes of the third N-by-N switching unit.
15. A switching topology as recited in claim 14 , further comprising a fifth N-by-N switching unit having N/2 nodes coupled to each of the first through fourth N-by-N switching units.
16. A switching topology as recited in claim 14 , further comprising an additional pair of N-by-N switching units, each of said additional pair of N-by-N switching units having N/2 nodes coupled to each of the third and fourth N-by-N switching units.
17. A switching topology as recited in claim 14 , wherein N is a power of 2.
18. A switching topology as recited in claim 14 , wherein N equals 2, and further comprising:
a fifth N-by-N switching unit having N/2 nodes coupled to each of the first through fourth N-by-N switching units.
19. A switching topology as recited in claim 14 , wherein N equals 2, and further comprising:
an additional pair of N-by-N switching units, each of said additional pair of N-by-N switching units having N/2 nodes coupled to each of the third and fourth N-by-N switching units.