Memory device with barrier layer
View Patent ↗A memory device may include a substrate, a dielectric layer formed on the substrate and a charge storage element formed on the dielectric layer. The memory device may also include an inter-gate dielectric formed on the charge storage element, a barrier layer formed on the inter-gate dielectric and a control gate formed on the barrier layer. The barrier layer prevents reaction between the control gate and the inter-gate dielectric.
1. A memory device, comprising:
a substrate;
a first dielectric layer formed on the substrate;
a charge storage element formed on the first dielectric layer;
a second dielectric layer formed on the charge storage element;
a conductive layer comprising ruthenium formed on the second dielectric layer; and
a control gate formed on the conductive layer, wherein the conductive layer acts as a barrier layer between the control gate and the second dielectric layer and does not act as a part of the charge storage element.
2. The memory device of claim 1 , wherein the conductive layer comprises ruthenium oxide.
3. The memory device of claim 2 , wherein the conductive layer has a thickness ranging from about 50 Å to about 500 Å and does not function to store charge for the memory device.
4. The memory device of claim 1 , wherein the first dielectric layer comprises silicon oxide, the charge storage element consists of a single layer of silicon nitride, the second dielectric layer comprises silicon oxide and the control gate comprises polycrystalline silicon.
5. The memory device of claim 1 , wherein the second dielectric layer comprises at least one of hafnium oxide, aluminum oxide or zirconium oxide.
6. The memory device of claim 1 , wherein the charge storage element comprises at least one of hafnium oxide or aluminum oxide.
7. The method of claim 1 , wherein the memory device includes a plurality of memory cells, each of the memory cells having a charge storage element configured to store charges representing two bits of information.
8. A non-volatile memory device, comprising:
a plurality of memory cells, each of the memory cells including:
a dielectric layer formed on a substrate,
a charge storage element formed on the dielectric layer,
an inter-gate dielectric formed on the charge storage element,
a barrier layer formed on the inter-gate dielectric, the barrier layer not being part of the charge storage element, and
a control gate formed on the barrier layer, wherein the barrier layer prevents reaction between the control gate and the inter-gate dielectric.
9. The non-volatile memory device of claim 8 , wherein the barrier layer comprises a conductive material.
10. The non-volatile memory device of claim 9 , wherein the barrier layer has a thickness ranging from about 50 Å to about 500 Å.
11. The non-volatile memory device of claim 8 , wherein the barrier layer comprises ruthenium.
12. The non-volatile memory device of claim 11 , wherein the barrier layer comprises ruthenium oxide and the control gate comprises silicon.
13. The non-volatile memory device of claim 8 , wherein the barrier layer comprises at least one of ruthenium, iridium, zinc or cadmium.
14. The non-volatile memory device of claim 8 , wherein the charge storage element comprises a single dielectric layer, the single dielectric layer being configured to store charges representing two bits of data.
15. The non-volatile memory device of claim 8 , wherein the charge storage element comprises polycrystalline silicon.
16. A memory device, comprising:
a substrate;
a first dielectric layer formed on the substrate;
a charge storage element formed on the first dielectric layer;
an inter-gate dielectric formed on the charge storage element;
a conductive layer formed on the inter-gate dielectric; and
a control gate formed on the conductive layer, and
where the conductive layer acts as a barrier to prevent reactions between the control gate and the inter-gate dielectric and the conductive layer does not act to store charge for the memory device.
17. The memory device of claim 16 , wherein the conductive layer comprises ruthenium oxide.
18. The memory device of claim 16 , wherein the conductive layer has a thickness ranging from about 50 Å to about 500 Å.
19. The memory device of claim 16 , wherein the conductive layer comprises ruthenium oxide, the control gate comprises silicon and the inter-gate dielectric comprises a material having a dielectric constant greater than about 3.9.
20. The memory device of claim 16 , wherein the memory device is configured to be programmed using Fowler-Nordheim programming or channel hot electron programming and erased using Fowler-Nordheim erasing.