Process for fabricating pad frame and integrated circuit package
View Patent ↗A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed layer on an exposed side of the contact pads and the dielectric material, applying a second metal layer on the metal seed layer, selectively etching the second metal layer and the metal seed layer to provide pad frame circuitry, and building up metal on selective portions of the pad frame circuitry to define a plurality of die connect pads separated by a second layer of dielectric material, the die connect pads being electrically connected to the contact pads by the pad frame circuitry.
1. A process for fabricating a pad frame for an integrated circuit package, the process comprising:
building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material;
depositing a metal seed layer on an exposed side of said contact pads and said dielectric material;
applying a second metal layer on said metal seed layer;
selectively etching said second metal layer and said metal seed layer to provide pad frame circuitry;
building up metal on selective portions of said pad frame circuitry to define a plurality of die connect pads separated by a second layer of dielectric material, said die connect pads being electrically connected to said contact pads by said pad frame circuitry.
2. The process according to claim 1 , wherein building up metal on selective portions of said first side of said substrate comprises:
selectively plating said metal on said first side of said substrate.
3. The process according to claim 1 , wherein building up metal on selective portions of said first side of said substrate comprises:
applying a photo-imageable dielectric material on a first side of said substrate;
exposing and developing said photo-imageable dielectric material to provide pits in said photo-imageable material in which said first side of said substrate is exposed;
plating metal on said first side of said substrate, in said pits in said photo-imageable material.
4. The process according to claim 1 , wherein plating metal on said first side of said substrate, in said pits comprises plating a plurality of metal layers in said pits to define said plurality of contact pads.
5. The process according to claim 1 , wherein depositing said metal seed layer on said exposed side of said contact pads and said dielectric material comprises electroless plating said metal seed layer.
6. The process according to claim 1 , wherein depositing said metal seed layer comprises sputter coating said exposed side of said contact pads and said dielectric material.
7. The process according to claim 1 , wherein applying said second metal layer on said metal seed layer comprises electrolytic plating.
8. The process according to claim 1 , wherein selectively etching said second metal layer and said metal seed layer to provide pad frame circuitry comprises:
applying a photo-imageable etching mask to an exposed surface of said second metal layer;
exposing and developing said etching mask to provide pits in said etching mask in which said second metal layer is exposed; and
etching said second metal layer and said metal seed layer.
9. The process according to claim 1 , wherein building up metal on selective portions of said pad frame circuitry comprises providing a plating mask on said pad frame circuitry followed by plating said die connect pads.
10. The process according to claim 1 , wherein building up metal on selective portions of said pad frame circuitry comprises providing a mask on said pad frame, solder paste printing said metal, reflowing and coining said die connect pads.
11. A process for fabricating an integrated circuit package comprising:
building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material;
depositing a metal seed layer on an exposed side of said contact pads and said dielectric material;
applying a second metal layer on said metal seed layer;
selectively etching said second metal layer and said metal seed layer to provide pad frame circuitry;
building up metal on selective portions of said pad frame circuitry to define a plurality of die connect pads separated by a second layer of dielectric material, said die connect pads being electrically connected to said contact pads by said pad frame circuitry;
flip-chip mounting a semiconductor die to said die connect pads such that pads of said semiconductor die are electrically connected to said die connect pads by a plurality of solder bump connectors;
providing an underfill material surrounding said solder ball connectors;
etching away said substrate to expose said contact pads; and
singulating said integrated circuit package.
12. The process according to claim 11 , further comprising molding in a molding material to encapsulate said semiconductor die, prior to etching away said substrate.
13. The process according to claim 11 , wherein building up metal on selective portions of said first side of said substrate comprises:
selectively plating said metal on said first side of said substrate.
14. The process according to claim 11 , wherein building up metal on selective portions of said first side of said substrate comprises:
applying a photo-imageable dielectric material on a first side of said substrate;
exposing and developing said photo-imageable dielectric material to provide pits in said photo-imageable material in which said first side of said substrate is exposed;
plating metal on said first side of said substrate, in said pits in said photo-imageable material.
15. The process according to claim 11 , wherein plating metal on said first side of said substrate, in said pits comprises plating a plurality of metal layers in said pits to define said plurality of contact pads.
16. The process according to claim 11 , wherein depositing said metal seed layer on said exposed side of said contact pads and said dielectric material comprises electroless plating said metal seed layer.
17. The process according to claim 11 , wherein depositing said metal seed layer comprises sputter coating said exposed side of said contact pads and said dielectric material.
18. The process according to claim 11 , wherein applying said second metal layer on said metal seed layer comprises electrolytic plating.
19. The process according to claim 11 , wherein selectively etching said second metal layer and said metal seed layer to provide pad frame circuitry comprises:
applying a photo-imageable etching mask to an exposed surface of said second metal layer;
exposing and developing said etching mask to provide pits in said etching mask in which said second metal layer is exposed; and
etching said second metal layer and said metal seed layer.
20. The process according to claim 11 , wherein building up metal on selective portions of said pad frame circuitry comprises providing a plating mask on said pad frame circuitry followed by plating said die connect pads.
21. The process according to claim 11 , wherein building up metal on selective portions of said pad frame circuitry comprises providing a mask on said pad frame, solder paste printing said metal, reflowing and coining said die connect pads.