Decoder with energization control circuit
A multistage decoder circuit has an error reduction stage that includes an adaptation circuit. The adaptation circuit provides adaptable error reduction as a function of bit error rate. The multistage decoder circuit has an energization control circuit that couples to the adaptation circuit. The energization control circuit controls an energization of the adaptation circuit as a function of actual or expected channel quality.
1. A multistage decoder circuit, comprising:
a first error reduction stage that includes an adaptation circuit that controls multiple filter taps that provide adaptable error reduction as a function of bit error rate; and
an energization control circuit that couples to the adaptation circuit, the multiple filter taps freezing based on a last adaptation when the energization control circuit shuts off energization of the adaptation circuit.
2. The multistage decoder circuit of claim 1 wherein the function of bit error rate comprises a count of a number of sectors read since a previous energization of the adaptation circuit.
3. The multistage decoder of claim 1 wherein the function of bit error rate comprises a moving average of past bit error rate.
4. The multistage decoder of claim 3 wherein the energization control circuit energizes the adaptation circuit when the moving average is less than a first bit error rate level.
5. The multistage decoder of claim 4 wherein the energization control circuit de-energizes the adaptation circuit when the moving average is more than a second bit error rate level.
6. The multistage decoder of claim 5 wherein the energization control circuit comprises a hysteretic control range between the first and second moving average threshold levels.
7. The multistage decoder of claim 1 wherein the energization control circuit sets the energization ON during an ON time interval at the start of reading a first file, and the control circuit sets the energization OFF during an OFF time interval after the ON time interval, reducing power consumption for adaptation after the start of reading the first file.
8. The multistage decoder of claim 7 wherein the energization remains set OFF during a reading of a second file after the first file.
9. The multistage decoder of claim 1 further comprising a battery providing energization to the energization control circuit.
10. The multistage decoder circuit of claim 1 wherein the first error reduction stage comprises an equalizing filter that has the multiple filter taps, and the adaptable error reduction comprises an adaptable frequency response of the equalizing filter.
11. The multistage decoder circuit of claim 10 , further comprising a second error reduction stage that includes a detector wherein the adaptable error reduction comprises an adaptable detection complexity of the detector.
12. The multistage decoder circuit of claim 1 wherein the multistage decoder circuit comprises a read channel for a data storage device.
13. A method, comprising:
providing a read counter with a read counter count and a read counter preset number;
incrementing the read counter count when a sector is read; and
shutting off adaptation energization provided to an adaptive error reduction stage that controls multiple filter taps as a function of a difference between the read counter count and the read counter preset number, the multiple filter taps freezing based on a last adaptation when the adaptation energy is shut off.
14. The method of claim 13 further comprising:
providing a quality monitor counter with a quality monitor count and a quality monitor change preset number;
comparing the quality monitor count to the quality monitor change preset; and
providing the adaptation energization to the adaptive error reduction stage if a change in the quality monitor count exceeds the quality monitor change present number.
15. The method of claim 13 further comprising:
saving noise predictive maximum likelihood detector tap settings if the adaptation energization is shut off.
16. A multistage decoder circuit, comprising:
a first error reduction stage that controls multiple filter taps and that includes an adaptation circuit that provides adaptable error reduction as a function of bit error rate; and
an energization control circuit that couples an energization control output to the adaptation circuit that controls an energization of the adaptation circuit, the multiple filter taps freezing based on a last adaptation when the energization control circuit shuts off energization of the adaptation circuit.
17. The multistage decoder circuit of claim 16 wherein the function of bit error rate comprises a count of a number of sectors read since a previous energization of the adaptation circuit.
18. The multistage decoder circuit of claim 16 wherein the function of bit error rate comprises a count of a quality monitor output.