A memory capable of reducing the memory cell size is provided. In this memory, a first gate electrode of a first selection transistor and a second gate electrode of a second selection transistor are provided integrally with a word line, and arranged to obliquely extend with respect to the longitudinal direction of a first impurity region on a region formed with memory cells and to intersect with the first impurity region on regions formed with the first selection transistor and the second selection transistor in plan view.
1. A memory comprising:
a memory cell array region including a plurality of memory cells arranged in the form of a matrix
a first selection transistor and a second selection transistor provided for the respective ones of said plurality of memory cells;
a first impurity region functioning as an electrode partially constituting each said memory cell while functioning also as one of source/drain regions of said first selection transistor and said second selection transistor;
a second impurity region functioning as the other one of said source/drain regions of said first selection transistor and said second selection transistor; and
a word line provided on said memory cell array region along said first impurity region, wherein
said first selection transistor and said second selection transistor share said second impurity region,
a first gate electrode of said first selection transistor and a second gate electrode of said second selection transistor are provided integrally with each other by the same said word line and arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on a region formed with said memory cells and to intersect with said first impurity region on regions formed with said first selection transistor and said second selection transistor in plan view, and
said first selection transistor and said second selection transistor divide said first impurity region.
2. The memory according to claim 1 , wherein
two said word lines provided along divided said first impurity region respectively are connected with each other through said first gate electrode and said second gate electrode.
3. The memory according to claim 1 , wherein
said first impurity region and said second impurity region are formed by performing ion implantation into a semiconductor substrate through said first gate electrode and said second gate electrode serving as masks.
4. The memory according to claim 1 , wherein
regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to extend along the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view, and
regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to extend along the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view.
5. The memory according to claim 1 , wherein
regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view, and
regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view.
6. The memory according to claim 5 , wherein
said regions of said first impurity region and said second impurity region at least in the vicinity of said portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to obliquely extend at an angle of not more than about 40° with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view, and
said regions of said first impurity region and said second impurity region at least in the vicinity of said portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to obliquely extend at an angle of not more than about 40° with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view.
7. The memory according to claim 5 , wherein
said regions of said first impurity region and said second impurity region at least in the vicinity of said portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to obliquely extend oppositely to the oblique longitudinal direction of said first gate electrode in plan view, and
said regions of said first impurity region and said second impurity region at least in the vicinity of said portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to obliquely extend oppositely to the oblique longitudinal direction of said second gate electrode in plan view.
8. The memory according to claim 5 , wherein
said first gate electrode and said second gate electrode adjacent to each other are connected with each other through a connecting portion,
an edge of said connecting portion opposite to said second impurity region and an edge of said first impurity region opposite to said word line on said region formed with said memory cells are substantially aligned with each other, and
an edge of said second impurity region opposite to said connecting portion and an edge of said word line opposite to said first impurity region on said region formed with said memory cells are substantially aligned with each other.
9. The memory according to claim 8 , wherein
said first gate electrode, said connecting portion and said second gate electrode are arranged to have U shapes in plan view, and
said first impurity region and said second impurity region on said regions formed with said first selection transistor and said second selection transistor are arranged to have inverted U shapes intersecting with said U shapes of said first gate electrode, said connecting portion and said second gate electrode in plan view.
10. The memory according to claim 1 , wherein
the width of said word line provided along said first impurity region in a direction substantially perpendicular to the longitudinal direction of said first impurity region on said region formed with said memory cells is smaller than the width of a portion around the center of said first gate electrode in a direction substantially perpendicular to the longitudinal direction of said first gate electrode and the width of a portion around the center of said second gate electrode in a direction substantially perpendicular to the longitudinal direction of said second gate electrode.
11. The memory according to claim 1 , wherein
the width of a portion of said first gate electrode connected with said word line in a direction substantially perpendicular to the longitudinal direction of said first gate electrode is smaller than the width of a portion around the center of said first gate electrode in said direction substantially perpendicular to the longitudinal direction of said first gate electrode, and
the width of a portion of said second gate electrode connected with said word line in a direction substantially perpendicular to the longitudinal direction of said second gate electrode is smaller than the width of a portion around the center of said second gate electrode in said direction substantially perpendicular to the longitudinal direction of said second gate electrode.
12. The memory according to claim 11 , wherein
two opposite sides of said first gate electrode include a portion having a first angle with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells and another portion having a second angle smaller than said first angle in plan view, and
two opposite sides of said second gate electrode include a portion having said first angle with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells and another portion having said second angle smaller than said first angle in plan view.
13. The memory according to claim 1 , wherein
said plurality of memory cells include single diodes respectively, and
said first impurity region of a first conductivity type functions as a common first electrode for said diodes of said plurality of memory cells.
14. A memory comprising:
a memory cell array region including a plurality of memory cells arranged in the form of a matrix;
a first selection transistor and a second selection transistor provided for the respective ones of said plurality of memory cells;
a first impurity region functioning as an electrode partially constituting each said memory cell while functioning also as one of source/drain regions of said first selection transistor and said second selection transistor;
a second impurity region functioning as the other one of said source/drain regions of said first selection transistor and said second selection transistor; and
a word line provided on said memory cell array region along said first impurity region, wherein
said first selection transistor and said second selection transistor share said second impurity region,
a first gate electrode of said first selection transistor and a second gate electrode of said second selection transistor are provided integrally with each other by the same said word line and arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on a region formed with said memory cells and to intersect with said first impurity region on regions formed with said first selection transistor and said second selection transistor in plan view,
said first selection transistor and said second selection transistor divide said first impurity region,
regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said first gate electrode on said region formed with said first selection transistor are arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view, and
regions of said first impurity region and said second impurity region at least in the vicinity of portions intersecting with said second gate electrode on said region formed with said second selection transistor are arranged to obliquely extend with respect to the longitudinal direction of said first impurity region on said region formed with said memory cells in plan view.