Bitline governed approach for programming non-volatile memory
In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.
1. A method of programming non-volatile storage, comprising:
applying a program voltage pulse to a control gate for a non-volatile storage element in order to program said non-volatile storage element, said program voltage pulse includes a first portion, a second portion and a third portion, said second portion includes a magnitude lower in comparison to said first portion and said third portion, said second portion occurs after said first portion and prior to said third portion; and
changing a bit line voltage for said non-volatile storage element during said second portion of said program voltage pulse.
2. A method according to claim 1 , wherein:
said magnitude of said second portion is non-zero; and
said first portion and said second portion have a same magnitude.
3. A method according to claim 1 , wherein:
said changing said bit line voltage includes changing said bit line voltage from an inhibit condition to a programming condition.
4. A method according to claim 1 , wherein:
said changing said bit line voltage includes lowering said bit line voltage from a non-zero voltage to a zero voltage.
5. A method according to claim 1 , further comprising:
applying a pre-charging voltage to said control gate prior to applying said program voltage pulse to said control gate.
6. A method according to claim 5 , wherein:
said magnitude of said second portion of said program voltage pulse is equal to said pre-charging voltage.
7. A method according to claim 5 , wherein:
said non-volatile storage element is a flash memory device.
8. A method according to claim 5 , wherein:
said non-volatile storage element is a NAND flash memory device.
9. A method according to claim 5 , wherein:
said non-volatile storage element is a multi-state flash memory device.
10. A method of programming non-volatile storage, comprising:
applying an inhibit voltage to a source/drain line for a non-volatile storage element;
applying a first program voltage to a gate line for said non-volatile storage element while applying said inhibit voltage to said source/drain line;
reducing said first program voltage to said gate line to a non-zero value while applying said inhibit voltage to said source/drain line;
applying a programming signal to said source/drain line while said first program voltage is reduced; and
raising said first program voltage to said gate line while applying said programming signal to said source/drain line.
11. A method according to claim 10 , wherein:
said inhibit voltage is a positive voltage; and
said programming signal is zero volts.
12. A method according to claim 10 , further comprising:
applying a pre-charging voltage to said gate line prior to applying said first program voltage to said gate line.
13. A method according to claim 10 , wherein:
said non-volatile storage element is a flash memory device.
14. A method according to claim 10 , wherein:
said non-volatile storage element is a NAND flash memory device.
15. A method according to claim 10 , wherein:
said non-volatile storage element is a multi-state flash memory device.
16. A method of programming a set of non-volatile storage elements, comprising:
applying a program voltage to a word line for a subset of said non-volatile storage elements arranged on a plurality to NAND strings, said NAND strings are associated with bit lines;
applying an inhibit condition as a bit line voltage for said bit lines;
applying a program pulse to said word line, said program pulse has a magnitude;
reducing said magnitude of said program pulse during said program pulse and while said inhibit condition is applied as said bit line voltage;
determining which of said subset of said non-volatile storage elements are to be programmed;
changing said bit line voltage for non-volatile storage elements that are to be programmed so that a program condition is applied as said bit line voltage, said changing said bit line voltage is performed while said magnitude of said program pulse is reduced; and
increasing said magnitude of said program pulse after said changing said bit line voltage.
17. A method according to claim 16 , wherein:
said step of determining is performed prior to said step of applying a program voltage.
18. A method according to claim 16 , further comprising:
applying a pre-charging voltage to said word line prior to applying said program voltage to said word line, said applying said inhibit condition is commenced concurrently with said applying said pre-charging voltage to said word line.
19. A method according to claim 16 , further comprising:
applying a boosting voltage to other word lines for said NAND strings.
20. A method according to claim 16 , wherein:
said inhibit condition is a positive voltage;
said program condition is a voltage lower in magnitude than said inhibit condition; and
program voltage is higher in magnitude than said inhibit condition.
21. A method according to claim 16 , wherein:
said non-volatile storage elements are flash memory devices.
22. A method according to claim 16 , wherein:
said non-volatile storage elements are NAND flash memory devices.
23. A method according to claim 16 , wherein:
said non-volatile storage elements are multi-state flash memory devices.