Phase change memory array having equalized resistance
View Patent ↗A memory includes memory cells, a first line coupled to the memory cells, and a second line coupled to the memory cells. A series resistance due of the first line plus the second line at each one of the memory cells is substantially equal.
1. An integrated circuit having a memory comprising:
resistive memory cells;
a first line coupled to the resistive memory cells; and
a second line coupled to the resistive memory cells,
wherein a series resistance of the first line plus the second line at each one of the resistive memory cells is substantially equal.
2. The integrated circuit of claim 1 , wherein the first line and the second line have substantially the same resistance per unit length.
3. The integrated circuit of claim 1 , wherein the first line and the second line are located in separate metallization layers.
4. The integrated circuit of claim 1 , wherein the first line and the second line are located in a same metallization layer.
5. The integrated circuit of claim 1 , wherein the resistive memory cells each comprise a phase-change element.
6. The integrated circuit of claim 1 , wherein the resistive memory cells each comprise a transistor coupled to a phase-change element, and wherein the transistor and the phase-change element for each one of the resistive memory cells are coupled between the first line and the second line.
7. A memory comprising:
an array of phase-change memory cells;
bit lines coupled to each of the phase-change memory cells; and
ground lines parallel to the bit lines and coupled to each of the phase-change memory cells,
wherein the bit lines are connected at a first side of the array of phase-change memory cells and the ground lines are connected at a second side of the array of phase-change memory cells opposite the first side, and
wherein the bit lines and the ground lines have substantially the same resistance/length.
8. The memory of claim 7 , wherein the bit lines are located in a first metallization layer and the ground lines are located in a second metallization layer.
9. The memory of claim 7 , wherein the bit lines and the ground lines are located in a same metallization layer.
10. The memory of claim 7 , wherein each phase-change memory cell comprises a transistor and a phase-change element coupled between the transistor and a bit line.
11. The memory of claim 7 , wherein each phase-change memory cell comprises a transistor and a phase change element coupled between the transistor and a ground line.
12. A method for fabricating a memory, the method comprising:
providing an array of phase-change memory cells;
providing bit lines coupled to each of the phase-change memory cells;
providing, ground lines parallel to the bit lines and coupled to each of the phase-change memory cells;
connecting the bit lines to a first side of the array of phase-change memory cells; and
connecting the ground lines to a second side of the array of phase-change memory cells opposite the first side,
wherein the bit lines and the ground lines have substantially the same resistance/length.
13. The memory of claim 12 , wherein providing the bit lines comprises providing the bit lines in a separate metallization layer from the ground lines.
14. The memory of claim 12 , wherein providing the ground lines comprises providing the ground lines in a same metallization layer as the bit lines.
15. The memory of claim 12 , wherein providing the array of phase-change memory cells comprises providing a transistor and a phase-change element between the transistor and a bit line for each phase-change memory cell.
16. The memory of claim 12 , wherein providing the array of phase-change memory cells comprises providing a transistor and a phase change element between the transistor and a ground line for each phase-change memory cell.