Scan stream sequencing for testing integrated circuits
View Patent ↗A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan stream. Each scan stream is represented by a table having a row corresponding to each scan data segment in the stream. Each row has four fields: a start address, a segment length, a start pad length and an end pad length. Scan streams consist of the bit sequence of segment data interposed by dummy data corresponding in length to the start pad and end pad lengths. Scan streams are interleaved by using the pad lengths to time the processing of scan data segments.
1. A scan sequencing module for an integrated circuit tester, the scan sequencing module comprising:
at least one memory which stores scan stream data, wherein the scan stream data includes a plurality of sequences of scan data segments not contiguously located in the at least one memory and associated link table data;
at least one memory controller coupled to the memory, wherein the plurality of scan data segments are retrieved from the memory as determined by the link table data; and
at least one stream controller coupled to the memory controller, wherein scan data segment bits or dummy data bits are transmitted to a device under test as determined by the link table data.
2. The scan sequencing module of claim 1 , wherein at least one data buffer is coupled between the stream controller and the scan memory controller.
3. The scan sequencing module of claim 1 , further comprising a global sequencer coupled to the stream controllers, wherein scan data is transmitted by the stream controllers in response to each scan increment signal received from the global sequencer.
4. The scan sequencing module of claim 1 wherein the at least one memory comprises means for storing scan stream data.
5. The scan sequencing module of claim 1 wherein the at least one memory controller comprises means for retrieving the scan stream data from the at least one memory.
6. The scan sequencing module of claim 1 wherein the at least one stream controller comprises means for transmitting the scan stream data bits to the device under test.
7. The scan sequencing module of claim 1 wherein said link table data comprises:
a pointer to each scan data segment;
a scan data segment length for each scan data segment;
a start pad length for each scan data segment; and
an end pad length for each scan data segment.
8. A scan sequencing module for an integrated circuit tester, the scan sequencing module comprising:
a means for storing scan stream data, wherein the scan stream data includes a plurality of sequences of scan data segments not contiguously located in the means for storing scan stream data and associated link table data;
a means for controlling said means for storing scan stream data coupled to the means for storing scan stream data, wherein the plurality of scan data segments are retrieved from the means for storing scan stream data as determining by the link table data; and
a means for controlling streams coupled to the means for storing scan stream data, wherein scan data segment bits or dummy data bits are transmitted to a device under test as determined by the link table data.