Clock buffer circuit having predetermined gain with bias circuit thereof
View Patent ↗Implementing maintenance of a higher speed with fewest possible additional circuits while suppressing deterioration in characteristics of a clock buffer caused by an offset voltage. In a clock buffer circuit comprising a differential amplifier including a pair of load resistances, a pair of differential stage transistors, a constant current source transistor for supplying an operating current to the differential stage transistors, and a bias circuit for supplying to the constant current source transistor a bias voltage according to the resistance value of the load resistances, the bias circuit generates the bias voltage so controlled that the voltage gain of the clock buffer circuit becomes a predetermined value with respect to a variation of the resistance value of the load resistances.
1. A clock buffer circuit comprising:
a differential amplifier circuit comprising:
two load resistances;
two differential stage transistors connected respectively to said load resistances;
two inputs connected respectively to gates of said differential stage transistors;
two outputs connected respectively to said differential stage transistors; and
a constant current source transistor connected to said differential stage transistors, for supplying an operating current to said differential stage transistors; and
a bias circuit for supplying to a gate of said constant current source transistor a bias voltage, wherein
said bias circuit generates said bias voltage such that a voltage gain of said clock buffer circuit becomes a predetermined value irrespective of a variation of the resistance value of said load resistances,
said bias circuit comprises a transistor connected to said constant current source transistor wherein the transistor is formed between a current mirror circuit and said constant current source transistor, and
a current synthesized from a current generated by application of a reference voltage to an internal resistor and a current generated by application of the reference voltage to an external reference resistor is fed as an input current to said current mirror circuit.
2. A clock buffer circuit comprising:
a differential amplifier circuit comprising:
two load resistances;
two differential stage transistors connected respectively to said load resistances;
two inputs connected respectively to gates of said differential stage transistors;
two outputs connected respectively to said differential stage transistors; and
a constant current source transistor connected to said differential stage transistors for supplying an operating current to said differential stage transistors; and
a bias circuit for supplying to a gate of said constant current source transistor a bias voltage, wherein
said bias circuit generates said bias voltage such that said operating current changes inversely proportional to a resistance value of said load resistances raised to a predetermined exponent greater than one but not greater than two.
3. A clock buffer circuit comprising:
a differential amplifier circuit comprising:
two load resistances;
two differential stage transistors connected respectively to said load resistances;
two inputs connected respectively to gates of said differential stage transistors;
two outputs connected respectively to said differential stage transistors; and
a constant current source transistor connected to said differential stage transistors for supplying an operating current to said differential stage transistors; and
a bias circuit for supplying to a gate of said constant current source transistor a bias voltage, wherein
said bias circuit generates said bias voltage such that said operating current changes inversely proportional to a resistance value of said load resistances raised to a power of two, thereby keeping a voltage gain of said clock buffer circuit to be constant.
4. The clock buffer circuit according to claim 2 , wherein said bias circuit comprises a transistor connected to said constant current source wherein the transistor is formed between a current mirror circuit and said constant current source transistor and a current synthesized from a current generated by application of a reference voltage to an internal resistor and a current generated by application of the reference voltage to an external reference resistor is fed as an input current to said current mirror circuit.
5. The clock buffer circuit according to claim 3 , wherein said bias circuit comprises a transistor connected to said constant current source wherein the transistor is formed between a current mirror circuit and said constant current source transistor and a current synthesized from a current generated by application of a reference voltage to an internal resistor and a current generated by application of the reference voltage to an external reference resistor is fed as an input current to said current mirror circuit.
6. The clock buffer circuit according to claim 1 , wherein said bias circuit comprises:
a first voltage-to-current conversion circuit for outputting a current that flows by applying a reference voltage to an internal resistor therein;
a second voltage-to-current conversion circuit for outputting a current that flows by applying the reference voltage to an external reference resistor therein;
a first current mirror circuit receiving an output current of said first voltage-to-current conversion circuit, for outputting a mirrored current at a predetermined mirror ratio;
a second current mirror circuit receiving an output current of said second voltage-to-current conversion circuit, for outputting a mirrored current at a predetermined mirror ratio; and
a transistor connected to said constant current source wherein the transistor is formed between a current mirror circuit and said constant current source transistor;
provided that a current obtained by subtracting the mirrored current output from said second current mirror circuit from a mirrored current output from said first current mirror circuit is passed through said transistor connected to said constant current source transistor through said current mirror circuit formed therebetween.
7. The clock buffer circuit according to claim 2 , wherein said bias circuit comprises:
a first voltage-to-current conversion circuit for outputting a current that flows by applying a reference voltage to an internal resistor therein;
a second voltage-to-current conversion circuit for outputting a current that flows by applying the reference voltage to an external reference resistor therein;
a first current mirror circuit receiving an output current of said first voltage-to-current conversion circuit, for outputting a mirrored current at a predetermined mirror ratio;
a second current mirror circuit receiving an output current of said second voltage-to-current conversion circuit, for outputting a mirrored current at a predetermined mirror ratio; and
a transistor connected to said constant current source transistor wherein the transistor is formed between a current mirror circuit and said constant current source transistor;
provided that a current obtained by subtracting the mirrored current output from said second current mirror circuit from a mirrored current output from said first current mirror circuit is passed through said transistor connected to said constant current source transistor through said current mirror circuit formed therebetween.
8. The clock buffer circuit according to claim 3 , wherein said bias circuit comprises:
a first voltage-to-current conversion circuit for outputting a current that flows by applying a reference voltage to an internal resistor therein;
a second voltage-to-current conversion circuit for outputting a current that flows by applying the reference voltage to an external reference resistor therein;
a first current mirror circuit receiving an output current of said first voltage-to-current conversion circuit, for outputting a mirrored current at a predetermined mirror ratio;
a second current mirror circuit receiving an output current of said second voltage-to-current conversion circuit, for outputting a mirrored current at a predetermined mirror ratio; and
a transistor connected to said constant current source transistor wherein the transistor is formed between a current mirror circuit and said constant current source transistor;
provided that a current obtained by subtracting the mirrored current output from said second current mirror circuit from a mirrored current output from said first current mirror circuit is passed through said transistor connected to said constant current source transistor through said current mirror circuit formed therebetween.
9. The clock buffer circuit according to claim 2 , wherein said bias circuit comprises a transistor connected to said constant current source transistor wherein the transistor is formed between a current mirror circuit and said constant current source transistor.
10. The clock buffer circuit according to claim 2 , wherein a current synthesized from a current generated by application of a reference voltage to an internal resistor and a current generated by application of the reference voltage to an external reference resistor is fed as an input current to a current mirror circuit.
11. The clock buffer circuit according to claim 3 , wherein said bias circuit comprises a transistor connected to said constant current source transistor wherein the transistor is formed between a current mirror circuit and said constant current source transistor.
12. The clock buffer circuit according to claim 3 , wherein a current synthesized from a current generated by application of a reference voltage to an internal resistor and a current generated by application of the reference voltage to an external reference resistor is fed as an input current to a current mirror circuit.
13. A clock buffer comprising a plurality of clock buffer circuits according to claim 1 , wherein:
said clock buffer circuits are coupled in series;
said clock buffer circuits are coupled without use of capacitive coupling;
said clock buffer circuits are coupled without use of a direct current bias circuit between said clock buffer circuits; and
said clock buffer circuits are coupled without use of a direct current feedback path between said clock buffer circuits.
14. A clock buffer comprising a plurality of clock buffer circuits according to claim 2 , wherein:
said clock buffer circuits are coupled in series;
said clock buffer circuits are coupled without use of capacitive coupling;
said clock buffer circuits are coupled without use of a direct current bias circuit between said clock buffer circuits; and
said clock buffer circuits are coupled without use of a direct current feedback path between said clock buffer circuits.
15. A clock buffer comprising a plurality of clock buffer circuits according to claim 3 , wherein:
said clock buffer circuits are coupled in series;
said clock buffer circuits arc coupled without use of capacitive coupling;
said clock buffer circuits are coupled without use of a direct current bias circuit between said clock buffer circuits; and
said clock buffer circuits are coupled without use of a direct current feedback path between said clock buffer circuits.