Granted Patent B2

US 7,378,827 · App. 11/211,199 · Granted May 27, 2008

Abstract

Claims (61)

1. A switching regulator for supplying a regulated output voltage to a load circuit in response to an applied direct current (DC) input voltage, the switching regulator comprising;

an error amplifier circuit including a comparator for generating an amplifier control signal in response to a portion of the regulated output voltage and a predetermined reference voltage, and an output stage for generating an amplifier output signal in response to the control signal and the applied DC input voltage;

and

an analog voltage ramp circuit including:

a current source for generating a first current;

a current divider for generating a second current in response to the first current, wherein the second current is lower than the first current;

an integrator circuit for generating a ramp voltage signal in response to the second current; and

an analog voltage clamp circuit for clamping the amplifier control signal to the ramp voltage signal until the ramp voltage signal increases to a final voltage level.

2. The switching regulator according to claim 1 , further comprising an output control circuit for controlling a power transistor in response to the amplifier output signal such that the regulated output signal is generated at a terminal of the power transistor.

3. The switching regulator according to claim 2 , wherein the output control circuit comprises an oscillator circuit for generating a oscillating ramp signal, and a pulse width modulator for generating a pulse signal in response to the oscillating ramp signal and the amplifier output signal, wherein the pulse signal is applied to a gate terminal of the power transistor.

4. The switching regulator according to claim 1 , wherein the current divider comprises:

a first current mirror for generating an intermediate current in response to the relatively high first current; and

a second current mirror for generating the second current in response to the intermediate current,

wherein the second current is substantially lower than the intermediate current, and the intermediate current is substantially lower than the first current.

5. The switching regulator according to claim 4 , wherein the integrator circuit is connected to the current divider such that the second current passes between the integrator circuit and the second current mirror.

6. The switching regulator according to claim 5 , wherein the integrator circuit comprises a Miller capacitor and means for causing the second current to gradually charge the Miller capacitor, whereby the gradually increasing charge on the Miller capacitor provides the ramp voltage signal.

7. The switching regulator according to claim 6 , wherein the clamp circuit includes means for drawing a current through the output stage of the error amplifier circuit until the ramp voltage signal increases to the final voltage level.

8. The switching regulator according to claim 4 , wherein the first current mirror comprises:

a first transistor connected in series with the current source between a first voltage source and a second voltage source, wherein a gate terminal of the first transistor is connected to the current source such that the first current passes through the first transistor;

a second transistor having a first terminal connected to the first voltage source and a gate terminal connected to the current source, wherein a size of the second transistor is selected such that the intermediate current is lower than the first current,

wherein the second current mirror comprises:

a third transistor having a first terminal and a gate terminal connected to a second terminal of the second transistor, and a second terminal connected to the second voltage source, and

a fourth transistor having a first terminal connected to the integrator circuit, a gate terminal connected to the second terminal of the second transistor, and a second terminal connected to the second voltage source.

9. The switching regulator according to claim 8 , wherein the integrator circuit comprises:

a fifth transistor having a first terminal connected to the first voltage source and a gate terminal connected to the current source, wherein a size of the fifth transistor is substantially equal to a size of the first transistor such that the first current passes through the fifth transistor;

a capacitor having a first terminal connected to a second terminal of the fifth transistor, and a second transistor;

a sixth transistor having a first terminal connected to the second terminal of the capacitor, and a second terminal connected to the second voltage source;

a seventh transistor having a first terminal connected to the first terminal of the capacitor, a gate terminal connected to the first terminal of the sixth transistor, and a second terminal connected to the second voltage source; and

an eighth transistor connected between the first terminal of the seventh transistor and a first terminal of the fourth transistor,

wherein respective gate terminals of the sixth transistor and the eighth transistor are connected to receive a reset control signal.

10. The switching regulator according to claim 9 , wherein the capacitor comprises a Miller capacitor.

11. The switching regulator according to claim 10 , wherein the analog voltage clamp circuit comprises:

a ninth transistor having a first terminal connected to the first voltage source and a gate terminal connected to the current source, wherein a size of the ninth transistor is substantially equal to a size of the first transistor such that the first current passes through the ninth transistor;

a tenth transistor having a first terminal and a gate terminal connected to a second terminal of the ninth transistor, and a second terminal connected to the second voltage source;

an eleventh transistor having a first terminal, a gate terminal connected to the second terminal of the ninth transistor, and a second terminal connected to the second voltage source;

a twelfth transistor having a first terminal connected to the first voltage source, a second terminal connected to the first terminal of the eleventh transistor, and a gate terminal connected to the first terminal of the capacitor; and

a thirteenth transistor having a gate terminal and first terminal connected to the output stage of the error amplifier, and a second terminal connected to the first terminal of the eleventh transistor.

12. The switching regulator according to claim 11 , wherein the output stage of the error amplifier comprises:

an amplifier current source; and

an output transistor having a gate terminal connected to the current source to the amplifier, and to the gate and first terminal of the thirteenth transistor,

wherein an amplifier current generated by the amplifier current source is lower than the first current passing through the ninth transistor.

13. A switching regulator for supplying a regulated output voltage to a load circuit, the switching regulator comprising:

amplifier means for generating an amplifier control signal in response to the regulated output voltage and a predetermined reference voltage; and

an analog soft-start circuit including:m

an analog voltage ramp circuit for generating a ramp voltage signal; and

an analog voltage clamp circuit for clamping the amplifier control signal to the ramp voltage signal until the ramp voltage signal increases to a predetermined voltage level, wherein the analog clamp circuit includes:

a current mirror for generating a predetermined clamp voltage;

a clamping element connected between the amplifier means and the current mirror such that at least a portion of the clamp voltage is drawn through the clamping circuit while the ramp voltage signal is less than the predetermined voltage level; and

a switch connected between a voltage source and the current mirror, the switch being controlled by the ramp voltage signal such that substantially all of the clamp voltage is drawn through the switch when the ramp voltage signal is equal to the predetermined voltage level.

14. The switching regulator according to claim 13 , wherein the current mirror comprises:

a ninth transistor having a first terminal connected to the voltage source and a gate terminal connected to a current source;

a tenth transistor having a first terminal and a gate terminal connected to a second terminal of the ninth transistor, and a second terminal connected to a second voltage source; and

an eleventh transistor having a first terminal, a gate terminal connected to the second terminal of the ninth transistor, and a second terminal connected to the second voltage source,

wherein the first terminal of the eleventh transistor is connected to the clamping element and the switch.

15. The switching regulator according to claim 14 , wherein the clamping element comprises an NMOS transistor having a gate terminal and a first terminal connected to the amplifier means, and a second terminal connected to the first terminal of the eleventh transistor.

16. The switching regulator according to claim 15 , wherein the switch comprises an NMOS transistor having a first terminal connected to the voltage source, a gate terminal connected to the analog voltage clamp circuit, and a second terminal connected to the first terminal of the eleventh transistor.

17. A switching regulator for supplying a regulated output voltage having a first current to a load circuit in response to an applied direct current (DC) input voltage, the switching regulator comprising:

means for generating an amplifier control signal in response to the regulated output voltage and a predetermined reference voltage, and for generating an amplifier output signal in response to the amplifier control signal and the applied DC input voltage;

means for generating a second current in response to the first current, wherein the second current is lower than the first current;

means for generating a ramp voltage signal in response to the second current; and

means for clamping the amplifier control signal to the ramp voltage signal until the ramp voltage signal increases to a predetermined voltage level.

Assignments (10)