NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.
1. A vertical NROM flash memory array comprising:
a substrate having a doped region of a different conductivity type than the substrate extending along the substrate, the doped region acting as a first source/drain region;
a plurality of oxide pillars extending from the first source/drain region;
a plurality of ultra-thin silicon body regions each formed along an opposing sidewall of an oxide pillar, each ultra-thin silicon body region being fully depleted;
a polysilicon material formed on top of each oxide pillar and each body region, the polysilicon material acting as a second source/drain region and having the same conductivity type as the first source/drain region;
a continuous oxide layer formed over the substrate, body regions, and second source/drain regions such that the oxide layer has a greater thickness along the substrate than in other areas;
a nitride-oxide layer formed over the oxide layer only on the opposing sides of each oxide pillar; and
a polysilicon control gate formed over each nitride-oxide layer wherein the control gate extends upwards to at least the top of each oxide pillar.
2. The memory array of claim 1 and further including a conductive wire coupling each adjacent second source/drain region on each oxide pillar.
3. The memory array of claim 1 wherein the first and second source/drain regions are n+ type conductive material.
4. The memory array of claim 1 wherein the array has a NOR type architecture.
5. The memory array of claim 1 wherein the function of each source/drain region depends on biasing.
6. The memory array of claim 1 wherein the ultra-thin silicon body regions are each less than 100 nm thick.
7. The memory array of claim 1 wherein the ultra-thin silicon body regions are formed by epitaxial regrowth.
8. A pair of vertical NROM flash memory transistors comprising:
a p-type substrate having a lower n+ doped source/drain region extending along the substrate surface;
a pillar comprising an insulation material extending from the lower source/drain region;
an ultra-thin silicon body formed along opposing sidewalls of the pillar, each silicon body being fully depleted;
an upper n+ source/drain region formed on top of the pillar and each silicon body;
a continuous oxide layer formed over the substrate, silicon bodies, and upper source/drain region such that the oxide layer has a greater thickness along the substrate than in other areas;
a pair of nitride-oxide layers, each layer formed over the oxide layer only on the opposing sidewalls of the oxide pillar; and
a gate formed over each nitride-oxide layer wherein each gate extends upwards to at least the top of the pillar.
9. The transistors of claim 8 wherein the upper source/drain region is formed from n+ doped polysilicon.
10. The transistors of claim 8 wherein the gate is coupled to word lines of other transistors in a memory array.
11. The transistors of claim 8 wherein the upper source/drain region is coupled to adjacent transistors through a conductive bonding to act as a bit line.
12. The transistors of claim 8 wherein the lower source/drain region is coupled to adjacent transistors.
13. An electronic system comprising:
a processor that generates control signals for the system; and
a memory device coupled to the processor for operating in response to the control signals and having a plurality of memory cells comprising:
a substrate having a lower doped source/drain region of a different conductivity than the substrate extending along the substrate;
a plurality of oxide pillars extending from the lower source/drain region;
a plurality of fully depleted, ultra-thin silicon body regions each formed along an opposing sidewall of each pillar;
a polysilicon material formed on top of each pillar and each body region, the polysilicon material acting as an upper source/drain region and having the same conductivity as the lower source/drain region;
a continuous oxide layer formed over the substrate, body regions, and upper source/drain regions such that the oxide layer has a greater thickness along the substrate than in other areas;
a nitride-oxide layer formed over the oxide layer only on the opposing sidewalls of each pillar; and
a gate formed over each nitride-oxide layer wherein each gate extends upwards to at least the top of each pillar.
14. The system of claim 13 wherein the nitride is a charge storage layer.
15. The system of claim 13 wherein the lower and upper source/drain regions are n+ regions and the substrate is p-type.
16. A memory device fabricated on a substrate comprising:
a doped lower source/drain region having a different conductivity than the substrate and extending along the substrate;
a plurality of oxide pillars extending from the lower source/drain region;
a fully depleted, ultra-thin silicon body region formed along each opposing sidewall of the pillars;
an upper source/drain region doped into silicon on top of each pillar and each body region;
a continuous oxide layer formed over the substrate, body regions, and upper source/drain regions such that the oxide layer has a greater thickness along the substrate than in other areas;
a nitride-oxide layer formed over the oxide layer only on the opposing sides of each oxide pillar; and
a gate formed over each nitride-oxide layer wherein each gate extends upwards to at least the top of each pillar.
17. The memory device of claim 16 wherein the memory array is coupled in a NAND architecture.
18. The memory device of claim 16 wherein the memory array is coupled in a NOR architecture.
19. The memory device of claim 16 wherein the function of each upper and lower source/drain region is determined by biasing of the regions.
20. The memory device of claim 16 wherein each nitride layer has two charge storage regions.