IP Library Granted Patent US 7,595,265
Granted Patent B2
US 7,595,265 · App. 11/212,998 · Granted Sep 29, 2009

Semiconductor device and method for forming a metal line in the semiconductor device

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Quick Facts
Patent No.
US 7,595,265
App. No.
11/212,998
Granted
Sep 29, 2009
Kind
B2
Abstract

Contact resistance of a semiconductor device may be reduced, and thereby the reliability of the semiconductor device may be enhanced, when a metal line is formed in a semiconductor device according to a method including: (i) forming a metal layer on a semiconductor substrate; (ii) forming a groove on an upper surface of the metal layer by etching the metal layer; (iii) etching the metal layer so as to form a groove-engraved lower metal line that is wider than the groove; (iv) forming an insulator layer covering the semiconductor substrate and the groove-engraved lower metal line; (v) etching the insulator layer so as to form a contact hole exposing the groove; and (vi) forming a contact electrode filling the contact hole and an upper metal line connected thereto, above the insulator layer.

Claims (33)

1. A method of forming a metal line in a semiconductor device, comprising:

forming a metal layer on a semiconductor substrate;

forming a groove in an upper surface of the metal layer by etching the metal layer;

etching the metal layer so as to form a lower metal line having a width greater than a width of the groove;

forming an insulator layer covering the semiconductor substrate and the lower metal line;

etching the insulator layer to form a contact hole exposing at least part of the groove and a top surface of the lower metal line; and

forming a contact electrode filling the contact hole and an upper metal line connected thereto above the insulator layer.

2. The method of claim 1 , wherein the metal layer has a thickness of about 4,000 Å-6,000 Å.

3. The method of claim 1 , wherein the groove of the metal layer has a depth of about 500 Å-1,500 Å.

4. The method of claim 1 , wherein the metal layer comprises aluminum (Al) and/or titanium nitride (TiN).

5. The method of claim 1 , wherein etching the metal layer comprises plasma etching the metal layer with a gas comprising BCl 3 and/or Cl 2 at an etch selectivity at least 1:1 with respect to an overlying photoresist.

6. The method of claim 5 , wherein:

the metal layer has a thickness of about 4,000 Å-6,000 Å; and

the groove of the metal layer has a depth of about 500 Å-1,500 Å.

7. A semiconductor device, comprising:

a semiconductor substrate;

a lower metal line on the semiconductor substrate and having a groove at a top surface thereof;

an insulator layer above the lower metal line having a contact hole therein exposing at least a part of the groove and a top surface of the lower metal line;

a contact electrode in the contact hole; and

an upper metal line in contact with the contact electrode.

8. The semiconductor device of claim 7 , wherein the lower metal line has a thickness of about 4,000 Å-6,000 Å.

9. The semiconductor device of claim 8 , wherein the lower metal line comprises aluminum (Al) and/or titanium nitride (TiN).

10. The semiconductor device of claim 8 , wherein the contact hole has a width of greater than a width of the groove.

11. The semiconductor device of claim 8 , wherein the groove of the lower metal line has a depth of about 500 Å-1,500 Å.

12. The semiconductor device of claim 11 , wherein:

the groove of the lower metal line has a depth of about 500 Å-1,500 Å.

13. A method, comprising:

partially etching a metal layer on a semiconductor substrate to form a plurality of grooves or indentations in an upper surface of the metal layer at a plurality of first locations, the grooves or indentations having a first width;

fully etching the metal layer at a plurality of second locations so as to form a plurality of lower metal lines having a second width, the second width being greater than the first width, and the second locations not coinciding with the first locations;

forming an insulator layer over the lower metal line; and

etching the insulator layer to form a plurality of contact holes exposing the indentation or at least part of the groove and a top surface of the metal line.

14. The method of claim 13 , further comprising forming a contact electrode filling the contact hole.

15. The method of claim 14 , further comprising forming an upper metal line electrically connected to the contact electrode contact electrode.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: DONGBU HITEK CO., LTD.
To: DSS TECHNOLOGY MANAGEMENT, INC.
Reel/Frame 033035/0680 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 21, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017821/0670 →
CHANGE OF NAME Recorded Jun 8, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017749/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2005
From: SHIM, JOON-BUM
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 016940/0966 →