Granted Patent B2

US 7,312,626 · App. 11/216,199 · Granted Dec 25, 2007

Assignee: Micron Technology, Inc.

Abstract

Claims (115)

1. A circuit, comprising:

an input node to receive an input signal for a CMOS transistor stack;

a first output node to deliver the input signal to a PMOS pull-up transistor of the CMOS transistor stack;

a second output node to deliver the input signal to an NMOS pull-down transistor of the CMOS transistor stack;

a first passive signal path between the input node and the first output node to pass an effective rising edge of the input signal and delay an effective falling edge of the input signal to a gate of the PMOS transistor; and

a second passive signal path between the input node and the second output node to delay the effective rising edge of the input signal and pass the effective falling edge of the input signal to a gate of the NMOS transistor.

2. The circuit of claim 1 , wherein each of the first and second passive signal paths includes a diode.

3. The circuit of claim 1 , wherein each of the first and second passive signal paths includes a diode and a resistor connected in parallel across the diode.

4. The circuit of claim 1 , wherein:

the effective rising edge for the PMOS transistor includes a PMOS threshold voltage crossed to transition the PMOS transistor from a conducting transistor channel to a non-conducting transistor channel;

the effective rising edge for the NMOS transistor includes an NMOS threshold voltage crossed to transition the NMOS transistor from a non-conducting transistor channel to a conducting transistor channel;

the effective falling edge for the NMOS transistor includes the NMOS threshold voltage crossed to transition the NMOS transistor from the conducting transistor channel to the non-conducting transistor channel; and

the effective falling edge for the PMOS transistor includes the PMOS threshold voltage crossed to transition the PMOS transistor from the non-conducting transistor channel to the conducting transistor channel.

5. The circuit of claim 1 , wherein the first and second signal paths are adapted to slow a discharge rate of a PMOS gate in comparison to a discharge rate of an NMOS gate, and to slow a charge rate of the NMOS gate in comparison to a charge rate of the PMOS gate.

6. A circuit, comprising:

an input node to receive an input signal for a CMOS transistor stack;

a first output node to deliver the input signal to a gate of a PMOS pull-up transistor of the CMOS transistor stack, the PMOS transistor having a PMOS threshold voltage below which the PMOS transistor does not conduct and at which the PMOS transistor begins to conduct and continues to conduct at potentials greater than the PMOS threshold voltage;

a first passive signal path between the input node and the first output node;

a second output node to deliver the input signal to a gate of an NMOS pull-down transistor of the CMOS transistor stack, the NMOS transistor having an NMOS threshold voltage below which the NMOS transistor does not conduct and at which the NMOS transistor begins to conduct and continues to conduct at potentials greater than the NMOS threshold voltage;

a second passive signal path between the input node and the second output node;

the second passive signal path being adapted to delay the rising edge of the input signal from crossing the NMOS threshold voltage until after the PMOS threshold voltage is crossed; and

the first passive signal path being adapted to delay the falling edge of the input signal from crossing the PMOS threshold voltage until after the NMOS threshold voltage is crossed.

7. The circuit of claim 6 , wherein each of the first and second passive signal paths includes a diode.

8. The circuit of claim 6 , wherein each of the first and second passive signal paths includes a diode and a resistor connected in parallel across the diode.

9. A circuit, comprising:

an input node to receive an input signal for a CMOS transistor stack;

a first output node to deliver the input signal to a gate of a PMOS pull-up transistor of the CMOS transistor stack;

a first signal path between the input node and the first output node;

a second output node to deliver the input signal to a gate of an NMOS pull-down transistor of the CMOS transistor stack;

a second signal path between the input node and the second output node;

the first signal path being adapted to charge the gate of the PMOS transistor to a logic high potential at a first charging rate and discharge the gate of the PMOS transistor to a logic low potential at a first discharging rate; and

the second signal path being adapted to charge the gate of the NMOS transistor to a logic high potential at a second charging rate slower than the first charging rate and to discharge the gate of the NMOS transistor to a logic low potential at a second discharging rate faster than the first discharging rate.

10. The circuit of claim 9 , wherein each of the first and second signal paths includes a diode.

11. The circuit of claim 9 , wherein each of the first and second signal paths includes a diode and a resistor connected in parallel across the diode.

12. A circuit, comprising:

an input node to receive an input signal for a CMOS transistor stack;

a first output node to deliver the input signal to a PMOS pull-up transistor of the CMOS transistor stack;

a second output node to deliver the input signal to an NMOS pull-down transistor of the CMOS transistor stack;

a first diode, including an anode connected to the input node and a cathode connected to a gate of the PMOS transistor; and

a second diode, including an anode connected to a gate of the NMOS transistor and a cathode connected to the input node.

13. The circuit of claim 12 , further comprising a first resistor connected in parallel across the first diode and a second resistor connected in parallel across the second diode, wherein the first resistor has a value chosen to provide a desired conductance when the first diode is reverse-biased and the second resistor has a value chosen to provide a desired conductance when the second diode is reverse-biased.

14. A circuit, comprising:

a CMOS inverter, including:

a PMOS pull-up transistor, including a PMOS gate, a PMOS source connected to a first reference potential line and a PMOS drain connected to an inverter output node; and

an NMOS pull-down transistor, including an NMOS gate, an NMOS drain connected to the inverter output node, and an NMOS source connected to a second reference potential line;

a first passive signal path between an input node and the PMOS gate, the first passive signal path including a first diode having an anode connected to the input node and a cathode connected to a gate of the PMOS transistor; and

a second passive signal path between the input node and the NMOS gate, the second passive signal path including a second diode having an anode connected to a gate of the NMOS transistor and a cathode connected to the input node.

15. The circuit of claim 14 , wherein the first passive signal path further includes a first resistor connected in parallel across the first diode, and the second passive signal path further includes a second resistor connected in parallel across the second diode, wherein the first resistor has a value chosen to provide a desired conductance when the first diode is reverse-biased and the second resistor has a value chosen to provide a desired conductance when the second diode is reverse-biased.

16. A device, comprising:

means for passing an effective rising edge of an input signal and delaying an effective falling edge of the input signal to a gate of a PMOS transistor through a first passive signal path extending from an input node to the gate of the PMOS transistor; and

means for delaying the effective rising edge of the input signal and passing the effective falling edge of the input signal to a gate of the NMOS transistor through a second passive signal path extending from the input node to the gate of the NMOS transistor.

17. The device of claim 16 , wherein:

the means for passing an effective rising edge of an input signal and delaying an effective falling edge of the input signal to a gate of a PMOS transistor through a first passive signal path includes a first diode having an anode connected to the input node and a cathode connected to the gate of the PMOS transistor; and

the means for delaying the effective rising edge of the input signal and passing the effective falling edge of the input signal to a gate of the NMOS transistor through a second passive signal path includes a second diode having an anode connected to the gate of the NMOS transistor and a cathode connected to the input node.

18. A device, comprising:

means for charging a gate of a PMOS transistor to a logic high potential at a first charging rate and a gate of an NMOS transistor to a logic high potential at a second charging rate slower than the first charging rate; and

means for discharging the gate of the PMOS transistor to a logic low potential at a first discharging rate and the gate of the NMOS transistor to a logic low potential at a second discharging rate faster than the first discharging rate.

19. The device of claim 18 , wherein:

the means for charging a gate of a PMOS transistor to a logic high potential at a first charging rate and a gate of an NMOS transistor to a logic high potential at a second charging rate slower than the first charging rate includes a forward-biased diode connected between an input node and the gate of the PMOS transistor and a reverse-biased diode connected between the input node and the gate of the NMOS transistor; and

the means for discharging the gate of the PMOS transistor to a logic low potential at a first discharging rate and the gate of the NMOS transistor to a logic low potential at a second discharging rate faster than the first discharging rate includes a forward-biased diode connected between the input node and the gate of the gate of the NMOS transistor and a reverse-biased diode connected between the input node and the gate of the PMOS transistor.

20. An integrated circuit structure, comprising:

a substrate;

a PMOS transistor on the substrate, the PMOS transistor including an n-type gate;

an NMOS transistor on the substrate, the NMOS transistor including an n-type gate;

a first diode with an n-type cathode integrated with the n-type gate of the PMOS transistor and a p-type anode electrically connected to an input node; and

a second diode with a p-type anode in contact with the n-type gate of the NMOS transistor and an n-type cathode electrically connected to the input node.

21. The structure of claim 20 , wherein the first and second diodes include horizontally-oriented diodes.

22. The structure of claim 20 , wherein the first and second diodes include vertically-oriented diodes.

23. The structure of claim 20 , further comprising a first resistive polysilicon region electrically connecting the n-type gate of the PMOS transistor to the input node and a second resistive polysilicon region electrically connecting the n-type gate of the NMOS transistor to the input node.

24. The structure of claim 23 , wherein the first and second diodes include horizontally-oriented diodes and the first and second resistive polysilicon regions include horizontally-oriented resistive polysilicon regions.

25. The structure of claim 23 , wherein the first and second diodes include vertically-oriented diodes and the first and second resistive polysilicon regions include vertically-oriented resistive polysilicon regions.

26. A method, comprising:

forming an input node to receive an input signal for a CMOS transistor stack;

forming a first output node to deliver the input signal to a PMOS pull-up transistor of the CMOS transistor stack;

forming a second output node to deliver the input signal to an NMOS pull-down transistor of the CMOS transistor stack;

forming a first passive signal path between the input node and the first output node to pass an effective rising edge of the input signal and delay an effective falling edge of the input signal to a gate of the PMOS transistor; and

forming a second passive signal path between the input node and the second output node to delay the effective rising edge of the input signal and pass the effective falling edge of the input signal to a gate of the NMOS transistor.

27. The method of claim 26 , wherein forming the first signal path includes forming a first diode and forming the second signal path includes forming a second diode.

28. The method of claim 26 , wherein forming the first signal path includes forming a first diode and a first resistor in parallel across the first diode, and forming the second signal path includes forming a second diode and a second resistor in parallel across the second diode.

29. A method, comprising:

forming an input node to receive an input signal for a CMOS transistor stack;

forming a first output node to deliver the input signal to a PMOS pull-up transistor of the CMOS transistor stack;

forming a second output node to deliver the input signal to an NMOS pull-down transistor of the CMOS transistor stack;

forming a first diode, including forming an anode connected to the input node and a cathode connected to a gate of the PMOS transistor; and

forming a second diode, including forming an anode connected to a gate of the NMOS transistor and a cathode connected to the input node.

30. The method of claim 29 , further comprising forming a first resistor in parallel across the first diode and forming a second resistor in parallel across the second diode.

31. A method for delivering a digital input signal to an inverter that includes a PMOS transistor and an NMOS transistor, the PMOS transistor having a PMOS gate and further having a conducting state and a non-conducting state, the NMOS transistor having an NMOS gate and further having a conducting state and a non-conducting state, the method comprising:

passing an effective rising edge of the digital input signal effective for changing the PMOS transistor from the conducting state to the non-conducting state to the PMOS gate, and delaying an effective falling edge of the digital input signal effective for changing the PMOS transistor from the non-conducting state to the conducting state to the PMOS gate; and

delaying the effective rising edge of the digital input signal effective for changing the NMOS transistor from the non-conducting state to the conducting state to the NMOS gate, and passing the effective falling edge of the digital input signal effective for changing the NMOS transistor from the conducting state to the non-conducting state to the NMOS gate.

32. The method of claim 31 , wherein:

passing an effective rising edge includes conducting the rising edge through a forward-biased diode in a first signal path to the gate of the PMOS transistor;

delaying an effective falling edge includes conducting the falling edge through the first signal path with a reverse-biased diode;

delaying the effective rising edge includes conducting the rising edge through a second signal path with a reverse-biased diode; and

passing the effective falling edge includes conducting the falling edge through a forward-biased diode in the second signal path.

33. A method, comprising:

delaying a rising edge of a digital input signal from crossing an NMOS threshold voltage until after a PMOS threshold voltage is crossed; and

delaying a falling edge of the digital input signal from crossing the PMOS threshold voltage until after the NMOS threshold voltage is crossed.

34. The method of claim 33 , wherein:

delaying a rising edge of a digital input signal from crossing the NMOS threshold voltage until after the PMOS threshold voltage is crossed includes charging a gate of the NMOS transistor at a charging rate slower than a rate for charging a gate of the PMOS transistor; and

delaying a falling edge of the digital input signal from crossing the PMOS threshold voltage until after the NMOS threshold voltage is crossed includes discharging the gate of the PMOS at a discharging rate slower than a rate for discharging the gate of the NMOS transistor.

35. A method, comprising:

charging a gate of a PMOS transistor to a logic high potential at a first charging rate and a gate of an NMOS transistor to a logic high potential at a second charging rate slower than the first charging rate; and

discharging the gate of the PMOS transistor to a logic low potential at a first discharging rate and the gate of the NMOS transistor to a logic low potential at a second discharging rate faster than the first discharging rate.

36. The method of claim 35 , wherein:

charging includes charging the gate of the PMOS transistor through a forward-biased diode; and

discharging includes discharging the gate of the NMOS transistor through a forward-biased diode.

37. A method, comprising:

in response to receiving a rising edge of a digital input signal at an input node for an inverter including a transistor stack with a PMOS pull-up transistor connected to an NMOS pull-down transistor, decreasing channel conductance through the PMOS pull-up transistor before increasing channel conductance through the NMOS pull-down transistor to pull a potential at an inverter output to a logic low potential; and

in response to receiving a falling edge of the digital input signal at the inverter input, decreasing channel conductance through the NMOS pull-down transistor before increasing channel conductance through the PMOS pull-up transistor to pull the potential at the inverter output to a logic high potential.

38. The method of claim 37 , wherein:

decreasing channel conductance through the PMOS pull-up transistor before increasing channel conductance through the NMOS pull-down transistor to pull a potential at an inverter output to a low potential includes charging a gate of the PMOS pull-up transistor to a logic high potential at a first charging rate and a gate of the NMOS pull-down transistor to a logic high potential at a second charging rate slower than the first charging rate; and

decreasing channel conductance through the NMOS pull-down transistor before increasing channel conductance through the PMOS pull-up transistor to pull the potential at the inverter output to a logic high potential includes discharging the gate of the PMOS pull-up transistor to a logic low potential at a first discharging rate and the gate of the NMOS pull-down transistor to a logic low potential at a second discharging rate faster than the first discharging rate.

39. The method of claim 37 , wherein:

decreasing channel conductance through the PMOS pull-up transistor includes charging a gate of the PMOS pull-up transistor through a forward-biased diode; and

decreasing channel conductance through the NMOS pull-down transistor includes discharging a gate of the NMOS pull-down transistor through a forward-biased diode.

Assignments (9)

Continuity (1)