Passive elements in MRAM embedded integrated circuits
View Patent ↗An integrated circuit device ( 300 ) comprises a substrate ( 301 ) and MRAM architecture ( 314 ) formed on the substrate ( 308 ). The MRAM architecture ( 314 ) includes a MRAM circuit ( 318 ) formed on the substrate ( 301 ); and a MRAM cell ( 316 ) coupled to and formed above the MRAM circuit ( 318 ). Additionally a passive device ( 320 ) is formed in conjunction with the MRAM cell ( 316 ). The passive device ( 320 ) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture ( 314 ) and the passive device ( 320 ) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate ( 404, 504 ), resulting in three-dimensional integration.
1. A method of forming an integrated circuit device on a substrate, said method comprising:
forming front-end layers of the device on the substrate;
forming, on the front-end layers of the device, at least one power component;
forming, on the front end layers of the device, a MRAM circuit;
forming back-end layers over at least a portion of the front-end layers;
forming, on the back end layers, a MRAM cell; and
forming a plurality of resistor elements on back end layer on which a feature of the MRAM cell is fabricated, a portion of the plurality of resistor elements comprising a resistor element formed on a Magnetic Tunnel Junction layer and wherein at least one of the portion of the plurality of resistor elements can be shorted to change the resistance of the resistor.
2. The method of claim 1 wherein the step of forming a plurality of resistor elements further comprises forming a capacitor comprising a top electrode, a bottom electrode and a dielectric between the top electrode and the bottom electrode formed on back end layers, wherein at least one of the backend layers where the capacitor is found is associated with a feature of the MRAM cell.
3. The method of claim 1 wherein the step of forming a plurality of resistor elements includes forming at least a first resistor element comprising a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the two ferromagnetic layers, wherein the resistance of the first resistor element can be set at a high state when the magnetization in the first ferromagnetic layer is anti-parallel to the magnetization in the second ferromagnetic layer and set to a low state when the magnetization in the first ferromagnetic layer is parallel to the magnetization in second ferromagnetic layer.