Test structure of semiconductor device

1. A test structure of a semiconductor device comprising:

a semiconductor substrate;

a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided; and

first and second pads electrically connected respectively to the silicided first and second junction regions for receiving an application of an electrical signal and outputting a detected signal, wherein the first and second pads are formed on the same level as the gate electrode or the semiconductor substrate.

2. The test structure of claim 1 , wherein at least some of the first and second pads formed on the same level as the gate electrode are formed on a field isolation region defining the first and second active regions.

3. The test structure of claim 2 , further comprising a first connecting portion connecting the first pad to the first active region and a second connecting portion connecting the second pad to the second active region.

4. The test structure of claim 3 , wherein the first and second connecting portions include wells having the same conductivity type as the first and second junction regions, insulating layers formed on the wells, and auxiliary pads that are electrically connected to the first and second pads.

5. The test structure of claim 3 , wherein the overall area of the first and second connecting portions is sized and positioned such that the resistance of the first and second connecting portions is smaller than the resistance of the transistor.

6. The test structure of claim 5 , wherein the resistance of the first and second connecting portions are 100 or more times smaller than the resistance of the transistor.

7. The test structure of claim 1 , wherein the first and second pads formed on the same level as the semiconductor substrate are well pads which are formed on a portion of lower parts of the first and second junction regions and have the same conductivity type as the first and second junction regions.

8. The test structure of claim 7 , wherein first and second pad active regions respectively included in the first and second active regions having the well pads formed thereon are connected to regions other than the first and second pad active regions of the first and second active regions through contact active regions that have a width having the margin resolution of a photolithography process.

9. The test structure of claim 1 , wherein the first pad is connected to a ground voltage, the second pad is connected to a positive voltage, and the gate electrode is connected to a voltage that disturbs channel formation.

10. A test structure of a semiconductor device comprising:

a semiconductor substrate;

a transistor array which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided;

first and second pads electrically connected respectively to the silicided first and second junction regions for receiving an application of an electrical signal and outputting a detected signal, wherein the first and second pads are formed on the same level as the gate electrode; and

first and second connecting portions which respectively connect the first and second pads to the first and second junction regions.

11. The test structure of claim 10 , wherein at least some of the first and second pads formed on the same level as the gate electrode are formed on a field isolation region defining the first and second active regions.

12. The test structure of claim 10 , wherein the first and second connecting portions include wells having the same conductivity type as the first and second junction regions, insulating layers formed on the wells, and auxiliary pads that are electrically connected to the first and second pads.

13. The test structure of claim 10 , wherein the overall area of the first and second connecting portions is sized and positioned such that the resistance of the first and second connecting portions is smaller than the resistance of the transistor.

14. The test structure of claim 13 , wherein the resistance of the first and second connecting portions are 100 or more times smaller than the resistance of the transistor.

15. The test structure of claim 10 , wherein the first and second active regions include first and second main active regions arranged in a cross-finger array and a plurality of first and second sub-active regions which are connected to the first and second main active regions, allowing the first and second active regions to be interconnected, and which are arranged between the first and second main active regions facing and opposite to each other, respectively, so that transistors constituting the transistor array are formed on the plurality of first and second sub-active regions; and

wherein the first and second connecting portions are formed on the first and second main active regions, respectively, the first and second connecting portions arranged in a cross-finger array.

16. The test structure of claim 15 , wherein each of the transistors constituting the transistor array includes a plurality of sub-transistors which are connected to one another in parallel, and wherein the first and second sub-active regions include first and second common sub-active regions, respectively, and a plurality of first and second branch sub-active regions respectively connecting the first and second common sub-active regions to constitute the plurality of sub-transistors which are connected to one another in parallel to form the transistors.

17. The test structure of claim 16 , wherein the first and second branch sub-active regions have a width having the margin resolution of a photolithography process.

18. The test structure of claim 15 , wherein the first and second main active regions are connected to the first and second sub-active regions through contact active regions that have a width having the margin resolution of a photolithography process.

19. The test structure of claim 16 , wherein gate electrodes of each transistor have a width having the margin resolution of a photolithography process.

20. The test structure of claim 10 , wherein the first pad is connected to a ground voltage, the second pad is connected to a positive voltage, and the gate electrode is connected to a voltage that disturbs channel formation.

21. A test structure of a semiconductor device comprising:

a semiconductor substrate;

a transistor array which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided; and

first and second pads electrically connected respectively to the silicided first and second junction regions for receiving an application of an electrical signal and outputting a detected signal, wherein the first and second pads are formed on the same level as the semiconductor substrate.

22. The test structure of claim 21 , wherein the first and second pads formed on the same level as the semiconductor substrate are well pads which are formed on a portion of lower parts of the first and second junction regions and have the same conductivity type as the first and second junction regions.

23. The test structure of claim 21 , wherein first and second pad active regions respectively included in the first and second active regions having the well pads formed thereon are connected to regions other than the first and second pad active regions of the first and second active regions through contact active regions that have a width having the margin resolution of a photolithography process.

24. The test structure of claim 21 , wherein the first and second active regions include first and second main active regions arranged in a cross-finger array and a plurality of first and second sub-active regions which are connected to the first and second main active regions, respectively, allowing the first and second active regions to be interconnected, and which are arranged between the first and second main active regions facing and opposite to each other, respectively, so that transistors constituting the transistor array are formed on the plurality of first and second sub-active regions.

25. The test structure of claim 21 , wherein each of the transistors constituting the transistor array includes a plurality of sub-transistors which are connected to one another in parallel, and wherein the first and second sub-active regions include first and second common sub-active regions, respectively, and a plurality of first and second branch sub-active regions respectively connecting the first and second common sub-active regions to constitute the plurality of sub-transistors which are connected to one another in parallel to form the transistors.

26. The test structure of claim 25 , wherein the first and second branch sub-active regions have a width having the margin resolution of a photolithography process.

27. The test structure of claim 25 , wherein gate electrodes of each transistor have a width having the margin resolution of a photolithography process.

28. The test structure of claim 21 , wherein the first pad is connected to a ground voltage, the second pad is connected to a positive voltage, and the gate electrode is connected to a voltage that disturbs channel formation.