High performance flash memory device capable of high density data storage
View Patent ↗A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.
1. A method of programming a nonvolatile memory array including an away of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, comprising:
receiving a programming window containing a predetermined number of bits that are to be programmed in the array;
determining which of the predetermined number of bits are to be programmed in the memory array;
simultaneously programming the predetermined number of bits to corresponding memory cells in the array; and
simultaneously verifying a programming state of the predetermined number of bits in the array.
2. The method of claim 1 , further comprising:
pre-charging bit lines associated with the predetermined number of bits prior to simultaneously programming the predetermined number of bits.
3. The method of claim 2 , wherein the pre-charging bit lines associated with the predetermined number of bits comprises pre-charging bit lines to a voltage corresponding to a voltage source.
4. The method of claim 1 , wherein the programming window includes 64 bits.
5. The method of claim 1 , wherein the programming window includes 128 bits.
6. The method of claim 1 , wherein the determining which of the predetermined number of bits are to be programmed in the away is based on an inverse programming method.
7. The method of claim 6 , wherein the inverse programming method includes:
determining whether the predetermined number of bits is greater than one half of the number of bits in the programming window, where bits in the programming window not included in the predetermined number of bits are the remaining bits;
simultaneously programming the memory cells in the array corresponding to the remaining bits in the programming window if it is determined that the predetermined number of bits is greater that one half of the number of bits in the programming window; and
setting an indication bit to a predetermined logic state indicative of whether the predetermined number of bits is greater than one half of the number of bits in the programming window.
8. The method of claim 1 , wherein the simultaneously verifying a programming state comprises simultaneously verifying a programming state for a number of program windows.
9. The method of claim 1 , wherein the simultaneously verifying includes:
determining whether the predetermined number of bits on the array are programmed; and wherein the method further comprises:
reprogramming any non-programmed bits in the predetermined number of bits.
10. The method of claim 1 , wherein the simultaneously verifying a programming state comprises simultaneously verifying a programming state for 256 bits.
11. The method of claim 1 , wherein the away of memory cells include SONOS (silicon-oxide-nitride-oxide-silicon) type NOR memory cells.
12. The method of claim 1 , wherein the charge storage element comprises a dielectric charge storage element configured to store at least two independent charges for each memory cell.
13. A memory device comprising:
at least one away of non-volatile memory cells;
a voltage supply component configured to generate a programming voltage for simultaneously programming a plurality of the memory cells, the voltage supply component including a DC-to-DC converter; and
control logic configured to simultaneously program the plurality of memory cells, where the plurality of memory cells corresponds to a programming window including a predetermined number of bits to be programmed.
14. The memory device of claim 13 , wherein the at least one array of non-volatile memory cells includes:
a plurality of bit lines each connected to source or drain regions of a plurality of the memory cells; and
a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of a plurality of the memory cells.
15. The memory device of claim 14 , wherein the memory cells include NOR-type memory cells.
16. The memory device of claim 14 , further comprising:
a plurality of sense amplifiers operatively connected to the plurality of bit lines, where the plurality of sense amplifiers are low-power sense amplifiers; and
control logic configured to simultaneously verify a number of bits in programmed memory cells by monitoring a threshold voltage for each memory cell with a corresponding one of the plurality of sense amplifiers.
17. The memory device of claim 13 , wherein the programming window includes 64 bits.
18. The memory device of claim 13 wherein the predetermined number of bits is 256 bits.
19. A memory device comprising:
a core array including at least one array of non-volatile memory cells, the at least one array comprising:
a plurality of bit lines each connected to source or drain regions of a plurality of the memory cells; and
a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of a plurality of the memory cells;
a plurality of sense amplifiers operatively connected to the plurality of bit lines for sensing a threshold voltage for memory cells connected to the bit lines;
a voltage supply component configured to generate a programming voltage for simultaneously programming a plurality of the memory cells, the voltage supply component including a DC-to-DC converter;
control logic configured to receive a programming window containing a predetermined number of bits that are to be programmed in the at least one array, and determine which of the predetermined number of bits are to be programmed in the memory array;
control logic configured to pre-charge bit lines associated with the predetermined number of bits;
control logic configured to simultaneously program the predetermined number of bits to corresponding memory cells in the array; and
control logic configured to simultaneously verify a programming state of the predetermined number of bits in the array.
20. A memory device comprising:
a core array including at least one array of non-volatile memory cells, the at least one array comprising:
a plurality of bit lines each connected to source or drain regions of a plurality of the memory cells; and
a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of a plurality of the memory cells;
control logic configured to receive a programming window containing a predetermined number of bits that are to be programmed in the at least one array, and determine which of the predetermined number of bits are to be programmed in the at least one array;
control logic configured to simultaneously program the predetermined number of bits to corresponding memory cells in the at least one array; and
control logic configured to simultaneously read a programming state of the predetermined number of bits in the at least one array.
21. The memory device of claim 20 , further comprising:
a plurality of sense amplifiers operatively connected to the plurality of bit lines, where the plurality of sense amplifiers are low-power sense amplifiers; and
control logic configured to simultaneously read a number of bits in programmed memory cells by monitoring a threshold voltage for each memory cell with a corresponding one of the plurality of sense amplifiers.