Methods of forming copper interconnect structures on semiconductor substrates
Methods of forming copper interconnect structures according to embodiments of the present invention include forming an electrically insulating layer having a recess therein on a semiconductor substrate and then forming a layer of copper having a thickness greater than about 3000 Å on an upper surface of the electrically insulating layer and in the recess. The layer of copper is then annealed. This annealing step may be a relatively low temperature anneal (i.e., “soft” anneal). After the initial anneal, the layer of copper is planarized for a sufficient duration to reduce a thickness of the layer of copper on the upper surface to a range from about 1000 Å to about 2000 Å. The planarized layer of copper is then annealed again and/or exposed to a plasma treatment. The duration and temperature of this step(s) (i.e., the total “thermal treatment”) is sufficient to cause the formation of grooves at grain boundaries within the layer of copper. Following this thermal treatment, the layer of copper is further planarized for a sufficient duration to remove the grooves and expose the upper surface of the electrically insulating layer and define a conductive copper pattern within the recess.
1 . A method of forming a copper interconnect structure, comprising the steps of:
forming an electrically insulating layer having a recess therein, on a substrate;
forming a layer of copper having a thickness greater than about 3000 ÿ on an upper surface of the electrically insulating layer and in the recess;
annealing the layer of copper; then
planarizing the layer of copper for a sufficient duration to reduce a thickness of the layer of copper on the upper surface to a range from about 1000 Å to about 2000 Å; then
annealing the planarized layer of copper for a sufficient duration to define grooves therein at grain boundaries within the layer of copper; and then
further planarizing the layer of copper for a sufficient duration to expose the upper surface and define a conductive copper pattern within the recess.
2 . The method of claim 1 , wherein said step of forming a layer of copper comprises electroplating a layer of copper onto the electrically insulating layer.
3 . The method of claim 1 , wherein said step of forming a layer of copper is preceded by a step of forming an electrically conductive barrier layer comprising tantalum in the recess.
4 . The method of claim 1 , wherein said step of annealing the layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 50° C. to about 200° C.
5 . The method of claim 3 , wherein said step of forming an electrically conductive barrier layer comprises depositing an electrically conductive barrier layer on the upper surface; and wherein said step of further planarizing the layer of copper comprises planarizing the layer of copper and the electrically conductive barrier layer in sequence to expose the upper surface.
6 . The method of claim 5 , wherein said step of annealing the layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 50° C. to about 200° C.
7 . The method of claim 1 , wherein said step of forming a layer of copper is preceded by a step of forming an electrically conductive barrier layer comprising a bilayer of tantalum and tantalum nitride in the recess.
8 . The method of claim 4 , wherein said step of annealing the planarized layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 200° C. to about 500° C.
9 . The method of claim 1 , wherein said step of annealing the planarized layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 200° C. to about 500° C.
10 . A method of forming a copper interconnect structure, comprising the steps of:
forming an electrically insulating layer having a recess therein on a substrate;
forming a layer of copper having a thickness greater than about 3000 Å on an upper surface of the electrically insulating layer and in the recess;
annealing the layer of copper; then
planarizing the layer of copper for a sufficient duration to reduce a thickness of the layer of copper on the upper surface to a range from about 1000 Å to about 2000 Å; then
plasma treating the layer of copper for a sufficient duration to define grooves therein at grain boundaries within the layer of copper; and then
further planarizing the layer of copper for a sufficient duration to expose the upper surface and define a conductive copper pattern within the recess.
11 . The method of claim 10 , wherein said step of forming a layer of copper comprises electroplating a layer of copper onto the electrically insulating layer.
12 . The method of claim 10 , wherein said step of forming a layer of copper is preceded by a step of forming an electrically conductive barrier layer comprising tantalum in the recess.
13 . The method of claim 10 , wherein said step of annealing the layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 50° C. to about 200° C.
14 . The method of claim 12 , wherein said step of forming an electrically conductive barrier layer comprises depositing an electrically conductive barrier layer on the upper surface; and wherein said step of further planarizing the layer of copper comprises planarizing the layer of copper and the electrically conductive barrier layer in sequence to expose the upper surface.
15 . The method of claim 14 , wherein said step of annealing the layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 50° C. to about 200° C.
16 . The method of claim 10 , wherein said step of forming a layer of copper is preceded by a step of forming an electrically conductive barrier layer comprising a bilayer of tantalum and tantalum nitride in the recess.
17 . A method of forming a copper interconnect structure, comprising the steps of:
forming an electrically insulating layer having a contact hole therein on a semiconductor substrate;
forming an electrically conductive barrier layer comprising tantalum on sidewalls of the contact hole;
electroplating a layer of copper having a thickness greater than about 3000 Å onto an upper surface of the electrically insulating layer and into the contact hole;
annealing the layer of copper; then
planarizing the layer of copper for a sufficient duration to reduce a thickness of the layer of copper on the upper surface to a range from about 1000 Å to about 2000 Å; then
annealing the planarized layer of copper for a sufficient duration to define grooves therein at grain boundaries within the layer of copper; and then
planarizing the layer of copper and the electrically conductive barrier layer in sequence to expose the upper surface and define a conductive copper pattern within the contact hole.
18 . The method of claim 17 , wherein said step of annealing the layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 50° C. to about 200° C.
19 . The method of claim 18 , wherein said step of annealing the planarized layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 200° C. to about 500° C.
20 . The method of claim 17 , wherein said step of annealing the planarized layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 200° C. to about 500° C.
21 . The method of claim 17 , wherein the electrically conductive barrier layer comprises a bilayer of tantalum and tantalum nitride.
22 . A method of forming a copper interconnect structure, comprising the steps of:
forming an electrically insulating layer having a recess therein, on a substrate;
forming a layer of copper on an upper surface of the electrically insulating layer and in the recess;
annealing the layer of copper; then
planarizing an upper surface of the layer of copper for a duration sufficient to remove at least 1000 Å therefrom, but insufficient to expose the electrically insulating layer; then
heat treating the planarized layer of copper for a sufficient duration to define grooves therein at grain boundaries within the layer of copper; and then
further planarizing the layer of copper for a sufficient duration to expose the upper surface and define a conductive copper pattern within the recess.
23 . The method of claim 22 , wherein said step of forming a layer of copper comprises electroplating a layer of copper onto the electrically insulating layer.
24 . The method of claim 22 , wherein said step of forming a layer of copper is preceded by a step of forming an electrically conductive barrier layer comprising tantalum in the recess.
25 . The method of claim 22 , wherein said step of annealing the layer of copper comprises heating the layer of copper in a process chamber having a temperature in a range from about 50° C. to about 200° C.
26 . The method of claim 22 , wherein said heat treating step comprises heating the planarized layer of copper in a process chamber having a temperature in a range from about 200° C. to about 500° C.