Strobe technique for recovering a clock in a digital signal

1. A method for extracting a clock signal from a digital signal, comprising:

applying a strobe to the digital signal, wherein said strobe comprises a plurality of strobe pulses;

storing the state of the digital signal at the time of strobe pulses of the strobe;

encoding the stored states as a digital word thereby identifying an edge time of a state change in the digital signal; and

determining an average edge time over a predetermined number of samples of the digital word.

2. The method according to claim 1 , further comprising:

storing the digital word in a memory location; and

using the average edge time as a pointer to the memory location.

3. The method according to claim 1 , further comprising adding a de-skew value to the average edge time to form an adjusted average edge time.

4. The method according to claim 3 , further comprising:

storing the digital word in a memory location; and

using the adjusted average edge time as a pointer to the memory location.

5. The method according to claim 4 , further comprising distributing the average edge time to a plurality of channels over a bus wherein the adjusted average edge time is used as a pointer to memory on a recipient channel of the plurality of channels.

6. The method according to claim 4 , further comprising:

comparing a data edge time the memory location addressed by the adjusted average edge time with expected data; and

providing a pass or fail indication as a result of the comparing.

7. The method according to claim 1 , wherein the strobe is applied to the digital signal by:

applying each pulse of the strobe as a latch-clock signal to a corresponding latch of a plurality of latches;

applying the digital signal to the input of each of the latches; and

receiving the state of the digital signal as output of each of the latches.

8. The method according to claim 1 , wherein the encoding results in a multi-bit word of which a first portion of the multi-bit word identifies the time of the state change and a second portion of the multi-bit word identifies the polarity of the state change.

9. The method according to claim 8 , further comprising de-multiplexing transmission of the multi-bit word to reduce a transmission rate thereof.

10. The method according to claim 1 , wherein the digital signal comprises a data signal of a device under test.

11. The method according to claim 1 , further comprising generating a strobe by:

applying an edge generator output signal to delay circuitry including a series of delay elements; and

providing a connection between each of the delay elements to receive a plurality of sequentially delayed copies of edges of the edge generator output signal, each of the delayed copies forming one of the strobe pulses.

12. The method according to claim 1 , wherein the delay circuitry is controlled by a delay locked loop and wherein the delay elements comprise controllable summing elements wherein the summing elements are tunable to correct delay line errors.

13. An apparatus for extracting a clock signal from a digital signal, comprising:

a plurality of increasing strobe delay elements in communication with an edge generator;

a plurality of latches, each having a clocking input communicatively connected to a corresponding one of the delay elements and having a data input receiving the data signal;

an encoder in communication with the plurality of latches, the encoder being adapted to transform information stored in the plurality of latches into a digital word representing edge time of the digital signal; and

averaging circuitry adapted to receive a plurality of the digital words from the encoder and determine the average thereof.

14. The apparatus according to claim 13 , wherein the averaging circuitry comprises:

an accumulator in communication with the encoder to receive the digital words;

a clock delay data register storing a de-skew value; and

adding circuitry in communication with the accumulator and the clock delay register, wherein the adding circuitry is adapted for adding the average edge time to the fixed de-skew value to form an extracted clock value.

15. The apparatus according to claim 14 , further comprising memory in communication with the encoder, wherein the memory is adapted for receiving and storing the digital words.

16. The apparatus according to claim 15 , further comprising dc-multiplexing circuitry in communication with the encoder and the memory wherein the de-multiplexing circuitry is adapted to reduce a rate of data transfer into the memory.

17. The apparatus according to claim 15 , wherein the digital signal is a data signal of a device under test.

18. The apparatus according to claim 15 , further comprising routing circuitry in communication with the averaging circuitry and the memory and adapted for addressing the memory using the extracted clock value as a pointer to the memory.

19. The apparatus according to claim 15 , wherein the routing circuitry comprises a clock bus in communication with the averaging circuitry and the memory, the routing circuitry being adapted for communication with a plurality of channels.

20. The apparatus according to claim 15 , further comprising comparison circuitry in communication with the memory and adapted for comparing an expected value corresponding to a specific clock time with a value of the data in the memory addressed by the extracted clock value.