Address generation method for combining multiple selection results
View Patent ↗A method in an integrated circuit for generating an address value having a contiguous address range from a first selection result and a second selection result each being an one-of-k selection result includes selecting multiple multiplication factors being power-of-two multiplication factors and the sum of the multiplication factors being equal to k; shifting the first selection result towards the most significant bit by each of the multiplication factors to generate multiple shifted input values where each shifted input value is shifted towards the most significant bit by one of the multiplication factors; adding the shifted input values and the second selection result; and generating the address value having a contiguous address range. The method can be extended to combine more than two selection results by applying the shifting and addition steps in a hierarchical manner.
1. A method in an integrated circuit for generating an address value having a contiguous address range from a plurality of selection results, each selection result being an one-of-k selection result, the method comprising:
(a) selecting a plurality of multiplication factors, the multiplication factors being power-of-two multiplication factors and the sum of the multiplication factors being equal to k;
(b) selecting a first selection result as a first input value;
(c) selecting a second selection result as a second input value;
(d) shifting using an ALU (arithmetic-logic unit) shifter implemented in the integrated circuit the first input value towards the most significant bit by each of the plurality of multiplication factors to generate a plurality of shifted input values, each shifted input value being shifted towards the most significant bit by one of the plurality of multiplication factors;
(e) adding using an ALU adder implemented in the integrated circuit the plurality of shifted input values and the second input value;
(f) generating an address output value;
(g) selecting the next selection result as the first input value;
(h) selecting the address output value as the second input value; and
(i) repeating the steps of (d) to (h) until all selection results have been selected,
wherein the address output value generated by the addition of the last selection result and the address output value generated by shifting using the ALU shifter and adding using the ALU adder of all previous selection results is the address value having a contiguous address range.
2. The method of claim 1 , wherein k is 12 and the plurality of multiplication factors comprises 8 and 4.
3. The method of claim 2 , wherein shifting using an ALU (arithmetic-logic unit) shifter implemented in the integrated circuit the first input value towards the most significant bit by each of the plurality of multiplication factors to generate a plurality of shifted input values comprises:
shifting using the ALU shifter the first input value towards the most significant bit by three places to generate a first shifted input value being a multiplied-by-8 value; and
shifting using the ALU shifter the first input value towards the most significant bit by two places to generate a second shifted input value being a multiplied-by-4 value.
4. A method in an integrated circuit for generating an address value having a contiguous address range from a first selection result and a second selection result, each selection result being an one-of-k selection result, the method comprising:
selecting a plurality of multiplication factors, the multiplication factors being power-of-two multiplication factors and the sum of the multiplication factors being equal to k;
shifting using an ALU (arithmetic-logic unit) shifter implemented in the integrated circuit the first selection result towards the most significant bit by each of the plurality of multiplication factors to generate a plurality of shifted input values, each shifted input value being shifted towards the most significant bit by one of the plurality of multiplication factors;
adding using an ALU adder implemented in the integrated circuit the plurality of shifted input values and the second selection result; and
generating an address output value being the address value having a contiguous address range by addition of the plurality of shifted input values and the second selection result.
5. The method of claim 4 , wherein k is 12 and the plurality of multiplication factors comprises 8 and 4.
6. The method of claim 5 , wherein shifting using an ALU (arithmetic-logic unit) shifter implemented in the integrated circuit the first selection result towards the most significant bit by each of the plurality of multiplication factors to generate a plurality of shifted input values comprises:
shifting using the ALU shifter the first selection result towards the most significant bit by three places to generate a first shifted input value being a multiplied-by-8 value; and
shifting using the ALU shifter the first selection result towards the most significant bit by two places to generate a second shifted input value being a multiplied-by-4 value.
7. A circuit in an integrated circuit for generating an address value having a contiguous address range from a plurality of selection results, each selection result being an one-of-k selection result, the circuit comprising:
one or more computation stages, each computation stage receiving a first input value and a second input value and generating an output value, each computation stage comprising an arithmetic-logic unit (ALU) shifter and an arithmetic-logic unit (ALU) adder,
wherein the ALU shifter applies a plurality of shifting operations to the first input value based on a plurality of multiplication factors, each multiplication factors being power-of-two multiplication factors and the sum of the multiplication factors being equal to k, the ALU shifter generating a plurality of shifted input values, each shifted input value being shifted towards the most significant bit by one of the plurality of multiplication factors, and
wherein the ALU adder adds the plurality of shifted input values and the second input value to generate the output value; and
the one or more computation stages comprising a first computation stage for receiving a first selection result and a second selection result as the first and second input values, wherein the second to last computation stages, if any, each receives the next selection result as the first input value and the output value of the previous computation stage as the second input value,
wherein the output value of the only or the last computation stage is the address value having a contiguous address range.
8. The circuit of claim 7 , wherein k is 12 and the plurality of multiplication factors comprises 8 and 4.
9. The circuit of claim 8 , wherein the ALU shifter shifts the first input value towards the most significant bit by three places to generate a first shifted input value being a multiplied-by-S value and shifts the first input value towards the most significant bit by two places to generate a second shifted input value being a multiplied-by-4 value.