Method to minimize formation of recess at surface planarized by chemical mechanical planarization
View Patent ↗When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having very different CMP removal rates or characteristics, the planarized surface may have excessively rough, dishing or recessing may take place, or one or more or the materials may be damaged. In structures in which planarity is important, these problems can be prevented by forming a capping layer on the patterned features, wherein the CMP removal rate of the material forming the capping layer is similar to the CMP removal rate of the dielectric fill.
1. A method for planarizing a surface, the method comprising:
depositing aluminum or an aluminum alloy;
depositing a second conductive material on and in contact with the aluminum or aluminum alloy;
patterning and etching the second conductive material and the aluminum or aluminum alloy to form patterned features;
depositing a dielectric material over and between the patterned features; and
polishing by a CMP process to coexpose the second conductive material and the dielectric material at a planarized surface, the CMP process adapted to remove the dielectric material,
wherein, during the polishing step, a removal rate of the second conductive material is between 50 percent and 150 percent of a removal rate of the dielectric fill.
2. The method of claim 1 wherein the dielectric material is an oxide, nitride, or oxynitride.
3. The method of claim 2 wherein the dielectric material is silicon dioxide.
4. The method of claim 1 wherein the second conductive material is titanium nitride.
5. The method of claim 1 wherein the features are substantially parallel rails.
6. The method of claim 5 wherein the parallel rails are conductors in a first memory level formed above a substrate.
7. The method of claim 6 wherein at least a second memory level is monolithically formed above the first.
8. The method of claim 1 wherein the second conductive material is deposited directly on the first conductive material.
9. The method of claim 8 wherein the second conductive material is no more than about 800 angstroms thick.
10. A method for forming a surface coexposing patterned features and dielectric material, the method comprising:
forming first features of a first conductive material and a conductive capping material on and in contact with the first conductive material;
forming dielectric fill between the first features; and
polishing by CMP to coexpose the dielectric fill and the conductive capping material,
wherein, during the polishing step the first conductive material has a lower removal rate than the conductive capping material,
wherein the first conductive material is tungsten.
11. The method of claim 10 wherein the conductive capping material is titanium nitride.
12. The method of claim 10 wherein the dielectric fill is an oxide, nitride, or oxynitride.
13. The method of claim 12 wherein the dielectric fill is silicon dioxide.
14. The method of claim 10 wherein the first features comprise a first plurality of substantially parallel rails.
15. The method of claim 14 wherein the rails are conductors within a first memory level formed above a substrate.
16. The method of claim 15 wherein at least a second memory level is monolithically formed above the first memory level in a monolithic three dimensional memory array.
17. The method of claim 10 wherein, during the polishing step, a removal rate of the conductive capping material is between 50 percent and 150 percent of a removal rate of the dielectric fill.
18. The method of claim 10 wherein the step of forming the first features comprises:
depositing the first conductive material;
depositing the conductive capping material on the first conductive material; and
patterning and etching the first conductive material and the conductive capping material to form the first features.
19. The method of claim 18 wherein the conductive capping material is deposited directly on the first conductive material.