IP Library Granted Patent US 7,510,883
Granted Patent B2
US 7,510,883 · App. 11/239,884 · Granted Mar 31, 2009

Magnetic tunnel junction temperature sensors and methods

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Quick Facts
Patent No.
US 7,510,883
App. No.
11/239,884
Granted
Mar 31, 2009
Kind
B2
Abstract

Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.

Claims (24)

1. A method of producing an integrated circuit, the method comprising:

providing a substrate having a heat source disposed in the substrate;

providing a conductive digit line;

providing a Magnetic Tunnel Junction (“MTJ”) temperature sensor over the heat source and the conductive digit line, wherein the MTJ temperature sensor comprises a MTJ core configured to output a current during operation thereof, wherein the value of the current varies based on a resistance value of the MTJ core and wherein the resistance value of the MTJ core varies as a function of the temperature of the heat source; and

providing a conductive bit line over the MTJ temperature sensor such that the MTJ temperature sensor is disposed between the conductive digit line and the conductive bit line.

2. A method according to claim 1 , wherein providing an MTJ temperature sensor over the heat source, further comprises:

depositing a first conductive MTJ electrode layer;

depositing a free layer, a tunnel barrier layer and a pinned layer on the first conductive MTJ electrode layer;

forming the MTJ core by patterning the free layer, the tunnel barrier layer and the pinned layer; and

depositing a second conductive MTJ electrode layer on the MTJ core.

3. A method according to claim 2 , the method further comprising:

depositing an inter-level dielectric layer over the second conductive MTJ electrode layer; and

depositing the conductive bit line over the inter-level dielectric layer.

4. A method of making an integrated circuit, comprising:

providing a substrate;

forming a heat source in the substrate from front end layers by a front end fabrication process, the heat source having a temperature; and

forming a Magnetic Tunnel Junction (“MTJ”) core from back end layers by a back end fabrication process after the front end fabrication process, the MTJ core having a resistance value which varies as a function of the temperature of the heat source and being configured to output a current during operation thereof which varies based on the resistance value of the MTJ core.

5. A method according to claim 4 , the method further comprising:

depositing a conductive digit line.

6. A method according to claim 5 , the method further comprising:

depositing an inter-level dielectric layer over the MTJ core; and

depositing a conductive bit line over the inter-level dielectric layer such that the MTJ core is disposed between the conductive digit line and the conductive bit line.

7. A method according to claim 6 , further comprising:

generating a field via at least one of the conductive digit line and the conductive bit line to set a temperature versus resistance characteristic of the MTJ core.

Assignments (6)
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 036084/0057 →
RELEASE OF SECURITY INTEREST Recorded Jul 30, 2010
From: CITIBANK, N.A.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 024767/0398 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 022366/0467 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2005
From: CHUNG, YOUNG SIR; BAIRD, ROBERT W.; DURLAM, MARK A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 017056/0252 →