Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
View Patent ↗A semiconductor device manufacturing method and a semiconductor device manufacturing apparatus which enable to detect an etching end-point with high accuracy are provided. In etching of a lower layer formed on a semiconductor wafer using a mask which comprises a plurality of patterns extending in a predetermined direction (line-and-space patterns) and contains at least one of a metal layer and an electrically-conductive metal compound layer, the surface of the semiconductor wafer is irradiated with inspection light, the etching is performed while monitoring the intensity of the polarized light component perpendicular to the predetermined extending direction of the line-and-space patterns and the etching is terminated at the time the intensity of the polarized light component reaches a reflected light intensity corresponding to a desired remaining thickness of the lower layer.
1. A semiconductor device manufacturing method comprising the steps of:
a first step for forming a polycrystalline silicon layer on a semiconductor substrate;
a second step for forming an electrically-conductive layer containing at least one of a metal and an electrically-conductive metal compound on the polycrystalline silicon layer;
a third step for forming a mask layer comprising plural patterns extending in a predetermined direction on the electrically-conductive layer;
a fourth step for patterning the electrically-conductive layer using the mask layer;
a fifth step for etching the polycrystalline silicon layer by plasma etching using a first etching gas and using the mask layer such that the polycrystalline silicon layer remains with a predetermined thickness; and
a sixth step for etching away the polycrystalline silicon layer with the predetermined thickness by plasma etching using a second etching gas different from the first etching gas and using the mask layer,
wherein, during said fifth step, a main surface of said semiconductor substrate is irradiated with inspection light and an end-point of said plasma etching using said first etching gas is determined on the basis of intensity of a polarized light component perpendicular to the predetermined direction contained in reflected light of said inspection light which is reflected from said main surface of said semiconductor substrate.
2. The semiconductor device manufacturing method as claimed in claim 1 , wherein said electrically-conductive layer contains tungsten (W).
3. The semiconductor device manufacturing method as claimed in claim 1 , further comprising a step for forming a silicon oxide layer on said semiconductor substrate prior to said first step and the surface of said silicon oxide layer is exposed by said sixth step.
4. The semiconductor device manufacturing method as claimed in claim 2 , further comprising a step for forming a silicon oxide layer on said semiconductor substrate prior to said first step and the surface of said silicon oxide layer is exposed by said sixth step.
5. The semiconductor device manufacturing method as claimed in claim 1 , wherein said first etching gas contains fluoro carbon and said second etching gas does not contain fluoro carbon.
6. The semiconductor device manufacturing method as claimed in claim 2 , wherein said first etching gas contains fluoro carbon and said second etching gas does not contain fluoro carbon.
7. The semiconductor device manufacturing method as claimed in claim 3 , wherein said first etching gas contains fluoro carbon and said second etching gas does not contain fluoro carbon.
8. The semiconductor device manufacturing method as claimed in claim 4 , wherein said first etching gas contains fluoro carbon and said second etching gas does not contain fluoro carbon.
9. The semiconductor device manufacturing method as claimed in claim 5 , wherein said polycrystalline silicon layer contains an N-type portion and a P-type portion.
10. The semiconductor device manufacturing method as claimed in claim 6 , wherein said polycrystalline silicon layer contains an N-type portion and a P-type portion.
11. The semiconductor device manufacturing method as claimed in claim 7 , wherein said polycrystalline silicon layer contains an N-type portion and a P-type portion.
12. The semiconductor device manufacturing method as claimed in claim 8 , wherein said polycrystalline silicon layer contains an N-type portion and a P-type portion.