Decoder for memory device with loading capacitor

1 . A decoder system for a memory device, the decoder system comprising:

a voltage pump for generating a boost voltage;

a voltage switch for coupling one of the boost voltage or a low voltage to a line of the memory device wherein the boost voltage has a higher voltage magnitude than the low voltage; and

a loading capacitor coupled to a node between the voltage pump and the voltage switch,

wherein the loading capacitor is a separate additional capacitor from any capacitor of the voltage pump such that a capacitance of the loading capacitor is determined by a parasitic capacitance at said line of the memory device.

2 . The decoder system of claim 1 , wherein the loading capacitor minimizes voltage dipping of the boost voltage that is switched to be applied on the line of the memory device.

3 . The decoder system of claim 1 , further comprising:

a local decoder for coupling one of the boost voltage or the low voltage from the voltage switch to the line of the memory device.

4 . The decoder system of claim 3 , further comprising:

a global decoder for generating control signals, wherein the local decoder couples one of the boost voltage or the low voltage to the line of the memory device in response to the control signals.

5 . The decoder system of claim 4 , wherein each local decoder includes:

a driving transistor, coupled between the voltage switch and the line of the memory device, for receiving one of the boost voltage or the low voltage; and

a pass transistor, coupled between the global decoder and the driving transistor, for turning on the driving transistor to couple one of the boost voltage or the low voltage to the line of the memory device in response to the control signals.

6 . The decoder system of claim 5 , wherein each local decoder further includes:

a pull-down transistor, coupled between a low voltage supply, the line of the memory device, and the global decoder, wherein the pull-down transistor is turned on to couple the low voltage of the low voltage supply to the line of the memory device when the driving transistor is turned off in response to the control signals.

7 . The decoder system of claim 1 , wherein the line of the memory device is a word-line of a flash memory device.

8 . The decoder system of claim 1 , wherein a capacitance of the loading capacitor is about four times the parasitic capacitance at the line of the memory device.

9 . The decoder system of claim 1 , further comprising:

a loading resistor coupled to the node between the voltage pump and the voltage switch,

wherein the loading resistor is a separate additional resistor from any resistor of the voltage pump.

10 - 14 . (canceled)

15 . A method for driving a line of a memory device, comprising:

generating a boost voltage from a voltage pump;

charging a loading capacitor coupled to the voltage pump when a low voltage is coupled to the line of the memory device, wherein the boost voltage has a higher voltage magnitude than the low voltage; and

coupling the loading capacitor to the line of the memory device when the voltage pump is switched to be applied on the line of the memory device,

wherein the loading capacitor is a separate additional capacitor from any capacitor of the voltage pump such that a capacitance of the loading capacitor is determined by a parasitic capacitance at said line of the memory device.

16 . The method of claim 15 , wherein the coupling of the loading capacitor minimizes voltage dipping of the boost voltage that is switched to be applied on the line of the memory device.

17 . The method of claim 16 , further comprising:

slowing down the voltage dipping of the boost voltage that is switched to be applied on the line of the memory device.

18 . The method of claim 15 , further comprising:

coupling one of the boost voltage or the low voltage to the line of the memory device in response to control signals from a global decoder.

19 . The method of claim 15 , wherein the line of the memory device is a word-line in a flash memory device.

20 . The method of claim 15 , wherein a capacitance of the loading capacitor is about four times the parasitic capacitance at the line of the memory device.