Converting dual port memory into 2 single port memories
View Patent ↗A circuit is configured as a splittable duplex memory cell or as a joinable single port memory pair based on the state of a programming layer. The programming layer has two states. In one state, the programming layer configures the circuit as a joinable single port memory pair. In the other state it configures the circuit as a splittable duplex memory cell. As such, the circuit can act as either a dual port memory cell or as two single port memory cells.
1. A system comprising:
a programming layer and a duplex memory cell comprising at least eight transistors comprising at least four enhancement mode transistors and at least four depletion mode transistors wherein the eight transistors and the programming layer are electrically connected to form a splittable duplex memory cell; and
a first port and a second port electrically connected to the splittable duplex memory cell to form a splittable dual port memory cell.
2. The system of claim 1 wherein at least one of the eight transistors has an insulated gate.
3. The system of claim 1 wherein at least one of the at least eight transistors is a CMOS transistor.
4. The system of claim 1 wherein at least one of the at least eight transistors is a Silicon-Germanium transistor.
5. The system of claim 1 wherein at least one of the at least eight transistors is a Gallium-Arsenide transistor.
6. The system of claim 1 wherein the programming layer comprises at least one fusible element.
7. The system of claim 1 wherein the programming layer comprises at least one volatile memory cell.
8. The system of claim 1 wherein the programming layer comprises at least erasable nonvolatile memory cell.
9. A system comprising:
a first memory cell and a first port electrically connected to form a first single port memory cell;
a second memory cell and a second port electrically connected to form a second single port memory cell; and
a programming layer electrically connected to the first single port memory cell and to the second single port memory cell to form a joinable single port memory cell pair.
10. The system of claim 9 wherein the first memory cell, second memory cell, or the programming layer comprises at least one transistor having an insulated gate.
11. The system of claim 9 wherein the first memory cell, second memory cell, or the programming layer comprises at least one CMOS transistor.
12. The system of claim 9 wherein the first memory cell, second memory cell, or the programming layer comprises at least one Silicon-Germanium transistor.
13. The system of claim 9 wherein the first memory cell, second memory cell, or the programming layer comprises at least one Gallium-Arsenide transistor.
14. The system of claim 9 wherein the programming layer comprises at least one fusible element.
15. The system of claim 9 wherein the programming layer comprises at least one volatile memory cell.
16. The system of claim 9 wherein the programming layer comprises at least erasable nonvolatile memory cell.
17. A method comprising:
supplying a first single port memory comprising a first memory cell and a first port;
supplying a second single port memory comprising a second memory cell and a second port; and
supplying a programming layer electrically connected to the first memory cell and the second memory cell thereby forming a splittable dual memory cell when the programming layer is in a first state and forming a joinable single port memory cell pair when the programming layer is in a second state.
18. The method of claim 17 further comprising placing the programming layer in the first state.
19. The method of claim 17 further comprising placing the programming layer in the second state.
20. The method of claim 17 further comprising using a CMOS semiconductor process to produce the first single port memory, second single port memory are supplied.