Method of fabricating silicon-based MEMS devices
View Patent ↗A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure with a residual mechanical stress of less than +/=100Mpa or simultaneously to produce a laminated structure having a mechanical stress of less than +/=100Mpa.
1. In a method of fabricating a silicon-based microstructure, the improvement comprising: depositing electrically conductive amorphous silicon doped in situ with first and second dopants, said first dopant being selected from the group consisting of arsenic, antimony, and bismuth; and said second dopant being phosphorus, and wherein said structure is a laminated structure with alternating first and second layers, each said first layer being doped with said first dopant and being in compressive mechanical stress and each said second layer being doped with said second dopant and being in tensile mechanical stress, and wherein said structure has a residual mechanical stress of less than +/−100 Mpa and a stress gradient of less than +/−20 Mpa/μm.
2. The method of claim 1 , wherein said first layer has a compressive stress of −0.01 to −400 Mpa, and said second layer has a tensile stress of+0.01 to+400 Mpa.
3. The method of claim 2 , wherein said first dopant is arsenic and said first layer is deposited in-situ at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr and from an arsine pressure of 0.01 to 50.0 mTorr to achieve a bulk resistivity of 0.01 to 1000 mohm.cm.
4. The method of claim 3 , wherein said second layer is deposited at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr and from a phosphine partial pressure of 0.1 to 5.0 mTorr.
5. The method of claim 2 , wherein said first dopant is antimony and said first layer is deposited in-situ at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr and from a stibine pressure of 0.01 to 50.0 mTorr to achieve a bulk resistivity of 0.01 to 1000 mohm.cm.
6. The method of claim 5 , wherein said second layer is deposited at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr and from a phosphine partial pressure of 0.1 to 5.0 mTorr.
7. The method of claim 2 , wherein said first dopant is bismuth and said first layer is deposited in-situ at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr and from an arsine pressure of 0.01 to 50.0 mTorr to achieve a bulk resistivity of 0.01 to 1000 mohm.cm.
8. The method of claim 7 , wherein said second layer is deposited at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr and from a phosphine partial pressure of 0.1 to 5.0 mTorr.
9. The method of claim 1 ,
wherein an integrated circuit is fabricated prior to depositing said electrically conductive amorphous silicon; and after fabricating said integrated circuit, a MEMS structure is integrated with said integrated circuit by carrying out said depositing of electrically conductive amorphous silicon.
10. The method of claim 9 wherein said amorphous silicon is deposited in-situ at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr, from a partial pressure of said first dopant 0.01 to 50.0 mTorr, and from a partial pressure of said second dopant of 0.1 to 5.0 mTorr.
11. In a method of fabricating a silicon-based microstructure, the improvement comprising: depositing electrically conductive amorphous silicon while simultaneously doping said amorphous silicon in situ with first and second dopants to produce a homogenous structure having a residual mechanical stress of less than +/=100Mpa and bulk resistivity of 0.01 to 1000 mohm.cms , said first dopant being selected from the group consisting of arsenic, antimony, and bismuth; and said second dopant being phosphorus.
12. The method of claim 11 , wherein said first dopant is arsenic and said amorphous silicon is deposited in-situ at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr, from an arsine pressure of 0.01 to 50.0 mTorr, and from a phosphine partial pressure of 0.1 to 5.0 mTorr.
13. The method of claim 11 , wherein said first dopant is antimony and said amorphous silicon is deposited in-situ at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr, from a stibine partial pressure of 0.01 to 50.0 mTorr, and from a phosphine partial pressure of 0.1 to 5.0 mTorr.
14. The method of claim 11 , wherein said first dopant is bismuth and said amorphous silicon is deposited in-situ at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr, from an bismuthine pressure of 0.01 to 50.0 mTorr, and from a phosphine partial pressure of 0.1 to 5.0 mTorr.
15. The method of claim 11 , wherein an integrated circuit is fabricated prior to depositing said electrically conductive amorphous silicon; and after fabricating said integrated circuit, a MEMS structure is integrated with said integrated circuit by carrying out said depositing of electrically conductive amorphous silicon.
16. The method of claim 15 , wherein said amorphous silicon is deposited in-situ at a temperature of 520 to 580° C. from a silane partial pressure of 100 to 5000 mTorr, from a partial pressure of said first dopant 0.01 to 50.0 mTorr, and from a partial pressure of said second dopant of 0.1 to 5.0 mTorr.