IP Library Granted Patent US 7,332,395
Granted Patent B2
US 7,332,395 · App. 11/255,972 · Granted Feb 19, 2008

Method of manufacturing a capacitor

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Quick Facts
Patent No.
US 7,332,395
App. No.
11/255,972
Granted
Feb 19, 2008
Kind
B2
Abstract

A method of manufacturing a stack capacitance type capacitor is provided, which prevents the problem that the capacitor cannot be formed because a lower electrode collapses with the external wall thereof exposed in forming the lower electrode of the capacitor in a deep hole formed in silicon oxide, and removing silicon oxide that is a support base material for the lower electrode using a solution containing hydrogen fluoride to expose the external wall of the lower electrode. According to the invention, the support base material in which a deep hole is formed is formed with an amorphous carbon film, the amorphous carbon film used as the support base material for the lower electrode is removed by dry etching after forming the lower electrode, and it is thereby possible to prevent the lower electrode from collapsing.

Claims (42)

1. A method of manufacturing a capacitor with a cylindrical lower electrode used in a semiconductor device, comprising the steps of:

(1) forming a first insulating film on a semiconductor board with word lines and bit lines formed thereon;

(2) providing a conductor plug connected to the board with a surface thereof exposed, in a predetermined position in the first insulating film;

(3) depositing a support base material in which the capacitor is to be formed;

(4) forming a thin film on a surface of the support base material, patterning the thin film, and forming a deep hole in the support base material using the patterned thin film as a mask;

(5) performing processing of cleaning the surface of the conductor plug exposed inside the deep hole, and depositing a material for the lower electrode of the capacitor on an entire surface including the inside of the deep hole;

(6) removing the material for the lower electrode formed on the surface of the support base material except the inside of the deep hole; and

(7) removing the support base material with the surface thereof exposed by dry etching, wherein the support base material is comprised of an amorphous carbon film formed by CVD.

2. A method of manufacturing a capacitor with a cylindrical lower electrode used in a semiconductor device, comprising the steps of:

(1) forming a first insulating film and a second insulating film laminated on the first insulating film on a semiconductor board with word lines and bit lines formed thereon;

(2) providing a conductor plug connected to the board with a surface thereof exposed, in a predetermined position in the first insulating film and the second insulating film;

(3) depositing a support base material in which the capacitor is to be formed;

(4) forming a thin film on a surface of the support base material, patterning the thin film, and forming a deep hole in the support base material using the patterned thin film as a mask;

(5) performing processing of cleaning the surface of the conductor plug exposed inside the deep hole, and depositing a material for the lower electrode of the capacitor on an entire surface including the inside of the deep hole;

(6) removing the material for the lower electrode formed on the surface of the support base material except the inside of the deep hole; and

(7) removing the support base material with the surface thereof exposed by dry etching, wherein the support base material is comprised of an amorphous carbon film formed by CVD.

3. A method of manufacturing a capacitor with a cylindrical lower electrode used in a semiconductor device, comprising:

(1) forming a first insulating film and a second insulating film laminated on the first insulating film on a semiconductor board with word lines and bit lines formed thereon;

(2) providing a conductor plug connected to the board with a surface thereof exposed, in a predetermined position in the first insulating film and the second insulating film;

(3) depositing a first support base material and a second support base material laminated on the first support base material in which the capacitor is to be formed;

(4) forming a thin film on a surface of the second support base material, patterning the thin film, and forming a deep hole in the first support base material and the second support base material using the patterned thin film as a mask;

(5) performing processing of cleaning the surface of the conductor plug exposed inside the deep hole, and depositing a material for the lower electrode of the capacitor on an entire surface including the inside of the deep hole;

(6) removing the material for the lower electrode formed on the surface of the support base material except the inside of the deep hole; and

(7) removing the second support base material with the surface thereof exposed by dry etching,

wherein the second support base material is comprised of an amorphous carbon film formed by CVD.

4. A method of manufacturing a capacitor with a cylindrical lower electrode used in a semiconductor device, comprising the steps of:

(1) forming a first insulating film on a semiconductor board with word lines and bit lines formed thereon;

(2) providing a conductor plug connected to the board with a surface thereof exposed, in a predetermined position in the first insulating film;

(3) depositing a support base material in which the capacitor is to be formed;

(4) forming a thin film on a surface of the support base material, patterning the thin film, and forming a deep hole in the support base material using the patterned thin film as a mask;

(5) performing processing of cleaning the surface of the conductor plug exposed inside the deep hole, and depositing a material for the lower electrode of the capacitor in the deep hole;

(6) removing the material for the lower electrode formed on the surface of the support base material except the inside of the deep hole; and

(7) removing the support base material with the surface thereof exposed by dry etching, wherein the support base material is comprised of an amorphous carbon film formed by CVD.

5. The method of manufacturing a capacitor according to claim 2 , wherein the second insulating film laminated on the first insulating film is silicon nitride.

6. The method of manufacturing a capacitor according to claim 3 , wherein the second insulating film laminated on the first insulating film is silicon nitride.

7. The method of manufacturing a capacitor according to claim 1 , wherein the thin film formed on the surface of the support base material is silicon oxide.

8. The method of manufacturing a capacitor according to claim 2 , wherein the thin film formed on the surface of the support base material is silicon oxide.

9. The method of manufacturing a capacitor according to claim 4 , wherein the thin film formed on the surface of the support base material is silicon oxide.

10. The method of manufacturing a capacitor according to claim 1 , wherein the deep hole formed in the support base material is formed by dry etching using ammonia (NH 3 ) as an etching gas.

11. The method of manufacturing a capacitor according to claim 2 , wherein the deep hole formed in the support base material is formed by dry etching using ammonia (NH 3 ) as an etching gas.

12. The method of manufacturing a capacitor according to claim 4 , wherein the deep hole formed in the support base material is formed by dry etching using ammonia (NH 3 ) as an etching gas.

13. The method of manufacturing a capacitor according to claim 3 , wherein the deep hole formed in the second support base material is formed by dry etching using ammonia (NH 3 ) as an etching gas.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →