Non-volatile memory device
View Patent ↗Operational information read out by a read-out sense amplifier ( 19 ) is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section ( 21 ) having a SRAM configuration and the second volatile memory section ( 23 ) configured with latch circuits, both sections respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section ( 21 ) in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section ( 23 ). Thus, the operational information is available in response to attributes of the operational information.
1. A non-volatile memory device comprising:
an array of non-volatile memory cells which stores a first and second operational information for the non-volatile memory device, wherein the first and second operational information are different; and
a volatile memory section which stores the first and second operational information only while power is being supplied to the non-volatile memory device, wherein the volatile memory section comprises:
a first volatile memory section having an array configuration from which the first operational information stored therein with address assignment is read out in response to individual address selections, the addresses linked with corresponding portions of the first operational information, wherein updated first operational information is stored in the array of non-volatile memory cells before the first volatile memory section is updated; and
a second volatile memory section, having a latch circuit configuration, comprising one or more latch circuits, and allowing immediate access to the second operational information stored therein in response to power-on, wherein the second volatile memory section constantly and repetitiously outputs in logically processable form all the second operational information stored therein.
2. A non-volatile memory device according to claim 1 further comprising a sense amplifier coupled to the volatile memory section, wherein the array of non-volatile memory cells includes a non-volatile memory section which stores the first and second operational information and is coupled to the sense amplifier, and wherein the sense amplifier reads the first and second operational information from the non-volatile memory section and provides the first and second operational information read therefrom to the first volatile memory section and the second volatile memory section in response to detection of power-on, initialization and/or a change of the first and second operational information stored in the non-volatile memory section.
3. A non-volatile memory device according to claim 1 , wherein the address assignment linked with the corresponding portions of the first operational information comprises address information defined in response to an internal operation which requires the corresponding portions of the operational information.
4. A non-volatile memory device according to claim 3 further comprising a sense amplifier coupled to the volatile memory section, wherein the array of non-volatile memory cells includes a non-volatile memory section which stores the first and second operational information and is coupled to the sense amplifier, and wherein the sense amplifier reads the first operational information to be stored in the first volatile memory section from the non-volatile memory section and provides the first operational information read therefrom to the first volatile memory section in response to detection of power-on, initialization and/or a change of the first operational information stored in the non-volatile memory section.
5. A non-volatile memory device according to claim 1 , wherein the first volatile memory section comprises:
a plurality of memory cells in the array configuration for storing the operation information, each of a predetermined number of the plurality of memory cells selectable in response to the address assignment; and
at least one common digit line commonly coupled to each of the predetermined number of the plurality of memory cells, and wherein the operational information stored in the plurality of memory cells is read out from the plurality of memory cells by being selected in response to the address assignment and provided on the at least one common digit line.
6. A non-volatile memory device according to claim 5 , wherein each of the plurality of memory cells comprise:
a memory section which stores the operational information; and
a selection switch section which is activated in response to the address assignment to connect the memory section to the at least one common digit line.
7. A non-volatile memory device according to claim 6 , wherein the array of non-volatile memory cells includes a non-volatile memory section which stores the first and second operational information in response to the address assignment, and wherein in response to power-on, initialization and/or a change of the first operational information stored in the non-volatile memory section the selection switch section connects the at least one common digit line to the first volatile memory section, thereby writing the first operational information from the non-volatile memory section to the first volatile memory section through the at least one common digit line.
8. A non-volatile memory device according to claim 1 , wherein the address assignment linked with the operational information to be stored in the first volatile memory section is defined in response to an external access operation.
9. A non-volatile memory device according to claim 8 , wherein the first operational information to be stored in the first volatile memory section comprises security information.
10. A non-volatile memory device according to claim 8 , wherein the first operational information to be stored in the first volatile memory section comprises write protect information, and wherein the address assignment is defined in accordance with address information which designates a region of the array of non-volatile memory cells subject to write protect control.
11. A non-volatile memory device according to claim 1 , further comprising a non-volatile memory section which stores the first and second operational information, and wherein the second volatile memory section comprises:
a latch section comprising the one or more latch circuits in which the second operational information is stored; and
a write-selection switch section which operably connects the latch section and the non-volatile memory section.
12. A non-volatile memory device according to claim 11 , wherein the second operational information is stored in the non-volatile memory section, and wherein in response to detecting power-on, initialization and/or a change of the second operational information stored in the non-volatile memory section, the write-selection switch section connects the non-volatile memory section to the second volatile memory section for writing the second operational information from the non-volatile memory section into the second volatile memory section.
13. A non-volatile memory device according to claim 1 , wherein all of the first and second operational information stored in the non-volatile memory section is transferred to either the first volatile memory section or the second volatile memory section in response to detection of power-on, initialization and/or a change of the first or second operational information stored in the non-volatile memory section.
14. A non-volatile memory device according to claim 1 , wherein the first and second volatile memory sections are arranged on a peripheral circuit region.
15. A non-volatile memory device according to claim 1 , wherein the second volatile memory section is arranged by a layout pattern with a second design rule, and wherein the first volatile memory section is arranged by a layout pattern with a first design rule finer than the second design rule by which the second volatile memory section is arranged.
16. A non-volatile memory device according to claim 1 , wherein a transistor device of a memory cell of the first volatile memory section is smaller than a transistor device of a memory cell of the second volatile memory section.
17. A non-volatile memory device according to claim 1 , wherein the first operational information comprises operational information necessary for executing predetermined internal operations of the non-volatile memory device.
18. A non-volatile memory device according to claim 1 , wherein the second operational information comprises operational information necessary for determining the operating conditions of the non-volatile memory device.