IP Library Granted Patent US 7,910,974
Granted Patent B2
US 7,910,974 · App. 11/261,176 · Granted Mar 22, 2011

Semiconductor device and method for fabricating thereof

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Quick Facts
Patent No.
US 7,910,974
App. No.
11/261,176
Granted
Mar 22, 2011
Kind
B2
Abstract

A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film.

Claims (6)

1. A semiconductor device comprising:

a semiconductor substrate; and

a cell region having a tunnel oxide film, a floating gate, a dielectric film and a control gate that are laminated in this order on the semiconductor substrate, the floating gate including a sidewall having a step formed from a single material on which the dielectric film is provided, wherein the sidewall of the floating gate has a plurality of steps on which the dielectric film is provided, wherein the step portions are provided as successively inward of the sidewall in the direction from the bottom of the floating gate to the top thereof wherein the steps are provided at intervals approximately equal to h/(n+1) where n is the number of steps and h is the height of the sidewall of the floating gate and wherein the steps are of equal length.

2. The semiconductor device as claimed in claim 1 , wherein the floating gate comprises one of polysilicon and amorphous silicon.

3. The semiconductor device as claimed in claim 1 , wherein the floating gate is doped with phosphorus.

4. The semiconductor device as claimed in claim 1 , wherein the dielectric film comprises one of an ON film having a silicon oxide film and a silicon nitride film laminated in this order and an ONO film having a silicon oxide film, a silicon nitride film and another silicon oxide film laminated in this order.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0174 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2005
From: UTSUNO, YUKIHIRO
To: SPANSION LLC
Reel/Frame 017157/0718 →