IP Library Granted Patent US 7,271,011
Granted Patent B2
US 7,271,011 · App. 11/262,054 · Granted Sep 18, 2007

Methods of implementing magnetic tunnel junction current sensors

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Quick Facts
Patent No.
US 7,271,011
App. No.
11/262,054
Granted
Sep 18, 2007
Kind
B2
Abstract

Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction (“MTJ”) core disposed between a first conductive layer and a second conductive layer. The MTJ core can be used to sense the first current and produce a second current based on the first current sensed at the MTJ core.

Claims (54)

1. A method of producing an integrated circuit, the method comprising:

providing a substrate comprising an active circuit component, wherein the active circuit component produces a first current;

providing a conductive digit line overlying in the substrate;

providing a Magnetic Tunnel Junction (“MTJ”) current sensor adjacent the active circuit component and the conductive digit line, wherein the MTJ current sensor comprises an MTJ core;

providing a conductive bit line adjacent the MTJ current sensor such that the MTJ current sensor is disposed between the conductive digit line and the conductive bit line; and

electrically coupling the active circuit component between the conductive digit line and the conductive bit line such that the MTJ core is designed to sense changes in the first current produced by the active circuit component and to produce a second current which indicates changes in the first current.

2. A method according to claim 1 , wherein the MTJ core is positioned to be electromagnetically coupled to said active circuit component, said conductive bit line and said conductive digit line.

3. A method according to claim 1 , wherein the active circuit component is disposed in a substrate and is formed from front end layers by a front end fabrication process, and wherein said MTJ core is formed above said active circuit component from back end layers by a back end fabrication process after the front end fabrication process.

4. A method according to claim 1 , wherein providing the MTJ current sensor over the active circuit component, further comprises:

depositing a first conductive MTJ electrode layer;

depositing a free layer, a tunnel barrier layer and a pinned layer on the first conductive MTJ electrode layer; and

patterning the free layer, the tunnel barrier layer and the pinned layer, wherein the patterned free layer, the patterned tunnel barrier layer and the patterned pinned layer comprise a MTJ core.

5. A method according to claim 4 , the method further comprising:

depositing a second conductive MTJ electrode layer on the MTJ core; and

depositing an interlevel dielectric layer over the second conductive MTJ electrode layer.

6. A method according to claim 5 , wherein the step of providing a conductive bit line comprises:

depositing the conductive bit line over the interlevel dielectric layer, wherein the conductive bit line and the MTJ core are not electrically connected, and wherein the conductive digit line and the MTJ core are not electrically connected.

7. A method of making an integrated circuit comprising a Magnetic Tunnel Junction (“MTJ”) current sensor, the method comprising:

providing a substrate having an active circuit component embedded therein, wherein the active circuit component produces a first current;

providing a digit line overlying the substrate;

providing an MTJ current sensor over the active circuit component;

providing a bit line overlying the substrate; and

electrically coupling the active circuit component between the bit line and the digit line, wherein the MTJ current sensor is disposed to sense changes in the first current and produce a second current based on the changes in the first current sensed by the MTJ current sensor.

8. A method according to claim 7 , wherein providing the MTJ current sensor over the active circuit component, comprises:

depositing a first conductive MTJ electrode layer;

depositing a free layer, a tunnel barrier layer and a pinned layer on the first conductive MTJ electrode layer;

patterning the free layer, the tunnel barrier layer and the pinned layer, wherein the patterned free layer, the patterned tunnel barrier layer and the patterned pinned layer comprise a MTJ core; and

depositing a second conductive MTJ electrode layer on the MTJ core.

9. A method according to claim 8 , the method further comprising:

depositing the digit line;

depositing an interlevel dielectric layer over the second conductive MTJ electrode layer; and

depositing the bit line over the interlevel dielectric layer.

10. A method according to claim 7 , wherein the MTJ current sensor comprises:

a dummy MRAM cell, comprising:

the digit line,

the bit line, and

a particular magnetic tunnel junction (“MTJ”) core, wherein said particular MTJ core responds to changes in the first current.

11. A method according to claim 10 , wherein providing the MTJ current sensor over the active circuit component, comprises:

forming a magnetic random access memory (“MRAM”) architecture on said substrate, said MRAM architecture comprising an MRAM cell array and the dummy MRAM cell.

12. A method according to claim 7 , wherein

the MTJ core is electromagnetically coupled to said active circuit component to sense changes in the first current and to produce the second current responsive to changes in the first current.

13. A method according to claim 7 , wherein providing the MTJ current sensor over the active circuit component, comprises:

providing a dummy MRAM cell comprising the digit line, the bit line, and a magnetic tunnel junction (“MTJ”) core, wherein said active circuit component is electrically coupled between the digit line and the bit line.

14. A method of making an integrated circuit comprising a Magnetic Tunnel Junction (“MTJ”) current sensor, the method comprising:

providing a substrate having an active circuit component embedded therein and a magnetic random access memory (“MRAM”) architecture formed thereon, said MRAM architecture comprising an array of MRAM cells, wherein the active circuit component produces a first current;

forming a digit line overlying the active circuit component;

forming a dummy MRAM cell comprising a magnetic tunnel junction (“MTJ”) core overlying the digit line, wherein said MTJ core is electromagnetically coupled to said active circuit component;

forming a bit line over the MTJ core, wherein the MTJ core is disposed between the digit line and the bit line; and

electrically coupling said active circuit component between the digit line and the bit line, and wherein said MTJ core is electromagnetically coupled to the digit line and the bit line such that the MTJ core senses changes in the first current and produces a second current based on the changes in the first current sensed by the MTJ current sensor.

15. A method according to claim 14 , wherein providing the MTJ current sensor over the active circuit component, comprises:

depositing a first conductive MTJ electrode layer;

depositing a free layer, a tunnel barrier layer and a pinned layer on the first conductive MTJ electrode layer;

patterning the free layer, the tunnel barrier layer and the pinned layer, wherein the patterned free layer, the patterned tunnel barrier layer and the patterned pinned layer comprise the MTJ core; and

depositing a second conductive MTJ electrode layer on the MTJ core.

Assignments (8)
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0704 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 036084/0057 →
RELEASE OF SECURITY INTEREST Recorded Jul 30, 2010
From: CITIBANK, N.A.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 024767/0398 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 022597/0062 →
SECURITY AGREEMENT Recorded Feb 16, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 020518/0215 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2005
From: CHUNG, YOUNG SIR; BAIRD, ROBERT W.; DURLAM, MARK A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 017166/0711 →