IP Library Granted Patent US 7,671,356
Granted Patent B2
US 7,671,356 · App. 11/265,275 · Granted Mar 2, 2010

Electrically rewritable non-volatile memory element and method of manufacturing the same

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Quick Facts
Patent No.
US 7,671,356
App. No.
11/265,275
Granted
Mar 2, 2010
Kind
B2
Abstract

A non-volatile memory element comprising a bottom electrode 12 , a top electrode 17 provided on the bottom electrode 12 , and a recording layer 18 containing phase change material connected between the bottom electrode 12 and the top electrode 17 . In accordance with this invention, the top electrode 17 is in contact with a growth initiation surface 18 a of the recording layer 17 . This structure can be obtained by forming the top electrode 17 before the recording layer 18 , resulting in a three-dimensional structure. This decreases heat dissipation to the bit line without increasing the thickness of the recording layer 18.

Claims (21)

1. A non-volatile memory element, comprising:

an insulating layer;

a bit line embedded into the insulating layer;

a hole selectively formed in the insulating layer to expose a part of the bit line;

a first electrode formed in the hole in contact with the part of the bit line to cap a whole of the part of the bit line;

a phase change material layer formed in contact with the first electrode;

a second electrode formed in contact with the phase change material layer; and

a transistor having an electrode electrically connected to the second electrode.

2. The non-volatile memory element as claimed in claim 1 , wherein the insulating layer has an upper surface and a side surface, the side surface of the insulating layer being defined by the hole, the part of the bit line being exposed from the side surface of the insulating film, the first electrode being formed along the side surface of the insulating layer to cap the part of the bit line.

3. A non-volatile memory element, comprising:

an insulating layer;

a bit line embedded into the insulating layer;

a hole selectively formed in the insulating layer to expose a part of the bit line;

a first electrode formed in the hole in contact with the part of the bit line to cap a whole of the part of the bit line;

a phase change material layer formed in contact with the first electrode; and

a second electrode formed in contact with the phase change material layer,

wherein the insulating layer has an upper surface and a side surface, the side surface of the insulating layer being defined by the hole, the part of the bit line being exposed from the side surface of the insulating film, the first electrode being formed along the side surface of the insulating layer to cap the part of the bit line, and the phase change material layer is formed in the hole in contact with the first electrode and elongated over a part of the upper surface of the insulating layer.

4. The non-volatile memory element as claimed in claim 3 , further comprising a lower insulating film, wherein the insulating layer is disposed on the lower insulating film, and the second electrode is buried in the lower insulating film and in contact with the phase change material layer at a bottom portion of the hole.

5. The non-volatile memory element as claimed in claim 1 , wherein a material of the first electrode is lower in thermal conductivity than the bit line.

6. The non-volatile memory element as claimed in claim 1 , wherein the electrode of the transistor is electrically connected to the second electrode without intervention of the first electrode and the bit line.

7. The non-volatile memory element as claimed in claim 6 , wherein the transistor has another electrode electrically connected to a wiring layer.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2006
From: OVONYX INC.
To: ELPIDA MEMORY, INC.
Reel/Frame 018094/0411 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2005
From: ASANO, ISAMU; LOWREY, TYLER A.
To: ELPIDA MEMORY, INC.
Reel/Frame 017187/0673 →