IP Library Patent Application 11271078
Patent Application
App. No. 11/271,078

Vertical diode doped with antimony to avoid or limit dopant diffusion

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Quick Facts
Patent No.
US None
App. No.
11/271,078
Abstract

Use of antimony as an n-type conductivity-enhancing dopant in semiconductor structures having a vertical dopant profile is described. Dopants tend to diffuse, and steep dopant gradients can be difficult to maintain. Specifically, when a silicon layer is doped with phosphorus or arsenic, both n-type dopants, dopant atoms tend to seek the surface as undoped silicon is deposited on top of the n-doped layer, rising through the undoped silicon during deposition. Antimony does not have this tendency, and also diffuses more slowly than either phosphorus or arsenic, and this is advantageously used to dope such structures.

Claims (31)

1 . A vertically oriented diode comprising:

a first layer of polycrystalline semiconductor material doped with antimony; and

a second layer of polycrystalline semiconductor material doped with a p-type dopant,

the first layer formed vertically above or below the second layer,

wherein the diode is a semiconductor junction diode comprising the first and second layers of polycrystalline semiconductor material.

2 . The diode of claim 1 wherein the polycrystalline semiconductor material of the first layer is silicon or a silicon alloy.

3 . The diode of claim 1 wherein the diode is a p-i-n diode or a p-n diode.

4 . The diode of claim 3 wherein a layer of intrinsic or lightly doped semiconductor material is between and in contact with the first and second layers.

5 . The diode of claim 1 wherein the first layer has a dopant concentration of at least 1×10 19 dopant atoms/cm 3 .

6 . The diode of claim 1 wherein the first layer is doped by in situ doping.

7 . The diode of claim 1 wherein the first layer is doped by ion implantation.

8 . The diode of claim 1 wherein the diode is disposed above a bottom conductor and below a top conductor and is in electrical contact with the bottom conductor and the top conductor.

9 . The diode of claim 8 wherein the bottom conductor does not comprise semiconductor material.

10 . The diode of claim 1 wherein the diode has a vertical height less than about 3000 angstroms.

11 . The diode of claim 10 wherein the diode has a vertical height less than about 1500 angstroms.

12 . The diode of claim 1 wherein the first layer is no more than about 500 angstroms thick.

13 . The diode of claim 1 wherein the diode is formed above a monocrystalline silicon substrate.

14 . The diode of claim 1 wherein the diode is a portion of a memory cell.

15 . The diode of claim 14 wherein the memory cell resides in a monolithic three dimensional memory array.

16 . A monolithic three dimensional memory array comprising:

a) a first memory level monolithically formed above a substrate, the first memory level comprising:

i) a first plurality of substantially parallel, substantially coplanar conductors;

ii) a first plurality of vertically oriented semiconductor junction diodes; and

iii) a second plurality of substantially parallel, substantially coplanar conductors, the second conductors above the first conductors,

wherein each of the first diodes is disposed between one of the first conductors and one of the second conductors, and

wherein each of the first diodes comprises a heavily doped n-type region doped with antimony, and

b) a second memory level monolithically formed above the first memory level.

17 . The monolithic three dimensional memory array of claim 16 wherein each first diode further comprises a heavily doped p-type region.

18 . The monolithic three dimensional memory array of claim 17 wherein each first diode further comprises an intrinsic or lightly doped region between the heavily doped p-type region and the heavily doped n-type region.

19 . The monolithic three dimensional memory array of claim 18 wherein the intrinsic or lightly doped region of each first diode is at least 600 angstroms thick.

20 . The monolithic three dimensional memory array of claim 19 wherein the intrinsic or lightly doped region of each first diode is at least 1000 angstroms thick.

Assignments (6)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0980 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTIVE MERGER TO ADD PAGES TO THE MERGER DOCUMENT PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 017544 FRAME 0769. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 2, 2007
From: MATRIX SEMICONDUCTOR, INC.
To: SANDISK 3D LLC
Reel/Frame 018950/0686 →
MERGER Recorded Apr 28, 2006
From: MATRIX SEMICONDUCTOR, INC.
To: SANDISK 3D LLC
Reel/Frame 017544/0769 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2005
From: KUMAR, TANMAY; HERNER, S. BRAD
To: MATRIX SEMICONDUCTOR
Reel/Frame 017129/0256 →