Embedded test circuitry and a method for testing a semiconductor device for breakdown, wearout or failure
View Patent ↗Reliability testing circuitry is built into the wafer or IC package in the form of one or more individual testers that use small-area transistors as DUTs. Stress can be applied to the DUTs in parallel and information about breakdown, wearout or failure can be obtained from the individual testers. Only a few pads are needed to test hundreds and even thousands of the DUTs of the individual testers. Testing of many DUTs may be performed using a simple power supply and a few probes.
1. An apparatus for testing a semiconductor device for breakdown, wearout or failure, the test circuitry being embedded in the semiconductor device, the test circuitry comprising:
at least two testers, each tester comprising:
a device under test (DUT) embedded in the semiconductor device;
a supply voltage connection for enabling a power supply that is external to the semiconductor device to be connected to the tester for supplying voltage to the DUT;
a current monitoring connection for enabling a current monitoring device to be electrically coupled to the current monitoring connection for monitoring a current passing through the DUT; and
a voltage regulator circuit comprising an operational amplifier (op-amp) having a non-inverting input that receives a reference voltage, the reference voltage being supplied to the op-amp from a global reference voltage supply that simultaneously supplies a reference voltage to all of the op-amps of all of the testers, each op-amp of each tester having an output that is electrically coupled to the DUT of the corresponding tester;
and wherein the supply voltage connections of the testers are electrically coupled such that the supply voltages are simultaneously supplied to the supply voltage connections of the testers.
2. The test circuitry of claim 1 , further comprising:
a plurality of testers for testing a plurality of locations in the semiconductor device for breakdown, wearout or failure, each of said plurality of testers being at least substantially identical to said two testers, and wherein the power supply is a global power supply that supplies a supply voltage to all of the supply voltage connections of all of the testers.
3. The test circuitry of claim 2 , further comprising:
a power supply network, and wherein the supply voltage connections of all of the testers are electrically coupled to the power supply network to enable the global power supply to simultaneously provide a supply voltage to all of the testers.
4. The test circuitry of claim 2 , wherein each of the DUTs of each of the testers is a transistor.
5. The test circuitry of claim 2 , wherein each of the DUTs of each of the testers is a capacitor.
6. The test circuitry of claim 1 , wherein the current monitoring connection of each of the testers comprises:
a current transmission gate (T-gate) electrically coupled to the DUT, the current T-gate transmitting the current of the DUT to a bus when the current T-gate is activated.
7. The test circuitry of claim 6 , wherein the current T-gates of the testers are activated serially such that no two current T-gates are transmitting simultaneously.
8. The test circuitry of claim 7 , wherein the current T-gates are activated by contents of a shift register.
9. The test circuitry of claim 1 , wherein each tester further comprises:
a voltage monitoring connection for enabling a voltage monitoring device to be electrically coupled to the voltage monitoring connection for monitoring a voltage of the DUT.
10. The test circuitry of claim 9 , further comprising:
a plurality of testers for testing a plurality of locations in the semiconductor device for breakdown, wearout or failure, each of said plurality of testers being at least substantially identical to said at least two testers, and wherein the power supply is a global power supply that supplies a supply voltage to all of the supply voltage connections of all of the testers.
11. The test circuitry of claim 10 , further comprising:
a power supply network, and wherein the supply voltage connections of all of the testers are electrically coupled to the power supply network to enable the global power supply to simultaneously provide a supply voltage to all of the testers.
12. The test circuitry of claim 9 , wherein each of the DUTs of each of the testers is a transistor.
13. The test circuitry of claim 1 , wherein the voltage measurement connection of each of the testers comprises:
a voltage transmission gate (T-gate) electrically coupled to the DUT, the voltage T-gate transmitting the voltage of the DUT to a bus when the voltage T-gate is activated.
14. The test circuitry of claim 13 , wherein the voltage T-gates are activated serially such that no two voltage T-gates are transmitting simultaneously.
15. The test circuitry of claim 14 , wherein the voltage T-gates are activated by contents of a shift register.
16. A method for testing a semiconductor device for breakdown, wearout or failure, comprising:
embedding testing circuitry in the semiconductor device, the test circuitry comprising at least two testers, each of the testers comprising:
a device under test (DUT) embedded in the semiconductor device;
a voltage supply connection for enabling a power supply that is external to the semiconductor device to be connected to the tester for supplying a supply voltage to the DUT;
a current monitoring connection for enabling a current monitoring device to be electrically coupled to the current monitoring connection for measuring a current passing through the DUT; and
a voltage regulator circuit comprising an operational amplifier (op-amp) having a non-inverting input that receives a reference voltage, the reference voltage being supplied to the op-amp from a global reference voltage supply that simultaneously supplies a reference voltage to all of the op-amps of all of the testers, each op-amp of each tester having an output that is electrically coupled to the DUT of the corresponding tester;
electrically coupling the external power supply to the voltage supply connection for supplying a supply voltage to the DUTs of the testers, and wherein the supply voltage connections of the testers are electrically coupled such that the supply voltages are simultaneously supplied to the supply voltage connections of the testers; and
electrically coupling a current monitoring device to the current monitoring connection for monitoring a current of the DUT.
17. The method of claim 16 , wherein the test circuitry embedded in the semiconductor device comprises a plurality of testers for testing a plurality of locations in the semiconductor device for breakdown, each of said plurality of testers being at least substantially identical to said two testers, and wherein the power supply is a global power supply that supplies a supply voltage to all of the supply voltage connections of all of the testers.