Voltage level detection circuit

1. A voltage level detection circuit comprising:

a pull-up unit including a plurality of pull-up means, each of the pull-up means supplying an internal voltage in response to a signal resulting from a logic operation of a voltage up control signal and a voltage down control signal;

a voltage division unit including a plurality of voltage dividers, each of the voltage dividers dividing the internal voltage from a corresponding one of the pull-up means;

a switching unit including a plurality of switching means, each of the switching means switching and supplying an output voltage from a corresponding one of the voltage dividers to an output node in response to a signal resulting from a logic operation of the voltage up control signal and voltage down control signal; and

a comparator for comparing the voltage at the output node with a predetermined reference voltage and outputting a voltage pumping enable signal according to a result of the comparison.

2. The voltage level detection circuit as set forth in claim 1 , wherein the plurality of pull-up means include:

a first pull-up means operated when the voltage up control signal is enabled;

a second pull-up means operated when the voltage down control signal is enabled; and

a third pull-up means operated when the voltage up control signal and the voltage down control signal are disabled.

3. The voltage level detection circuit as set forth in claim 2 , wherein:

the first pull-up means is a first PMOS transistor which is operated in response to an inverted signal of the voltage up control signal;

the second pull-up means is a second PMOS transistor which is operated in response to an inverted signal of the voltage down control signal; and

the third pull-up means is a third PMOS transistor which is operated in response to a signal resulting from an OR operation of the voltage up control signal and voltage down control signal.

4. The voltage level detection circuit as set forth in claim 2 , wherein the plurality of voltage dividers include:

a first voltage divider for dividing the internal voltage from the first pull-up means;

a second voltage divider for dividing the internal voltage from the second pull-up means; and

a third voltage divider for dividing the internal voltage from the third pull-up means,

wherein a ratio of the internal voltage to the output voltage from each of the voltage dividers is higher in the order of the second voltage divider, third voltage divider and first voltage divider.

5. The voltage level detection circuit as set forth in claim 1 , wherein the plurality of switching means include:

a first switching means operated when the voltage up control signal is enabled;

a second switching means operated when the voltage down control signal is enabled; and

a third switching means operated when the voltage up control signal and the voltage down control signal are disabled.

6. The voltage level detection circuit as set forth in claim 5 , wherein:

the first switching means is a first NMOS transistor which is operated in response to the voltage up control signal;

the second switching means is a second NMOS transistor which is operated in response to the voltage down control signal; and

the third switching means is a third NMOS transistor which is operated in response to a signal resulting from a NOR operation of the voltage up control signal and voltage down control signal.

7. The voltage level detection circuit as set forth in claim 1 , wherein the voltage pumping enable signal is enabled when the voltage at the output node is lower than the predetermined reference voltage.