Single poly BiCMOS flash cell with floating body
View Patent ↗A BiCMOS integrated circuit (IC) includes a floating gate-type non-volatile memory (NVM) device that uses the polycrystalline silicon gate of a CMOS FET and the P-base and N-emitter diffusions of a bipolar transistor to provide an isolated P-type body and N-type source/drain diffusions. The P-body diffusion of the NVM device is isolated from a P-substrate by an N-well, thus facilitating the use of reduced positive and negative voltage levels to produce the onset of Fowler-Nordheim tunneling without the need for a triple-well structure. The polysilicon gate structure is formed on a suitable gate oxide over the P-body. The source/drain diffusions, which like the N-emitter diffusions of the bipolar transistor have no LDD, produce a reduced field drop across the gate oxide to allow Fowler-Nordheim tunneling from the source side.
1. A BiCMOS integrated circuit (IC) comprising:
a substrate of a first conductivity type, the substrate having a first doping concentration;
a first well region of a second conductivity type disposed in the substrate and having a second doping concentration;
a first body region of the first conductivity type disposed in the first well region, the first body region having a third doping concentration that is at least five times higher than the second doping concentration;
a gate dielectric disposed on the first body region;
a control gate disposed on the gate dielectric;
source and drain regions of the second conductivity type disposed in the first body region on opposite sides of the control gate, the source and drain regions having a fourth doping concentration that is higher than the third doping concentration;
a second body region disposed in the first well region of the first conductivity type disposed and having the third doping concentration; and
a plate portion disposed over the second body region and being connected to the control gate,
wherein the plate portion and second body region form a coupling capacitor.
2. The BiCMOS IC according to claim 1 , wherein the fourth doping concentration of the body region is at least ten times higher than the second doping concentration.
3. The BiCMOS IC according to claim 1 , wherein the source and drain regions do not include lightly doped drain structures.
4. The BiCMOS IC according to claim 1 , wherein both a portion of each of the source and drain regions located under a side edge of the control gate and a second portion of said each source and drain regions located away from the side edge of the control gate have the fourth doping concentration.
5. The BiCMOS IC according to claim 1 , wherein the control gate and the plate portion comprise an integral polycrystalline silicon structure.
6. The BICMOS IC according to claim 1 , further comprising a bipolar transistor comprising:
a third well region of the second conductivity type disposed in the substrate and has the first doping concentration;
a base region of the first conductivity type disposed in the third well region, the base region having the third doping concentration; and
an emitter region of the second conductivity type disposed in the base region, the emitter region having the fourth doping concentration.
7. The BiCMOS IC according to claim 6 , wherein the bipolar transistor further comprises a collector contact region formed in the third well region and spaced from the base region, wherein the collector contact region has a sixth doping concentration that is less than the fourth doping concentration.
8. A BiCMOS integrated circuit (IC) comprising:
a substrate of a first conductivity type, the substrate having a first doping concentration;
a first well region of a second conductivity type disposed in the substrate and having a second doping concentration;
a first body region of the first conductivity type disposed in the first well region, the first body region having a third doping concentration that is at least five times higher than the second doping concentration;
a gate dielectric disposed on the first body region;
a control gate disposed on the gate dielectric;
source and drain regions of the second conductivity type disposed in the first body region on opposite sides of the control gate, the source and drain regions having a fourth doping concentration that is higher than the third doping concentration;
a CMOS field-effect transistor (FET) comprising:
a second well region of the first conductivity type disposed in the substrate and having a fifth doping concentration that is greater than the first doping concentration;
a second gate dielectric disposed on the second well region;
a second control gate disposed on the second gate dielectric; and
second source and drain regions of the second conductivity type disposed in the second well region on opposite sides of the control gate, each of the source and drain regions having a lightly-doped drain (LDD) region located adjacent to the second control gate, and a heavily-doped region located away from the second control gate, wherein the heavily doped regions of the second source and drain regions have a sixth doping concentration that is less than the fourth doping concentration.
9. The BiCMOS IC according to claim 8 ,
wherein the second gate dielectric of the CMOS FET and the first gate dielectric have a substantially identical thickness and composition, and
wherein the second control gate and the first control gate have a substantially identical thickness and conductivity.
10. A BiCMOS integrated circuit (IC) comprising:
a substrate of a first conductivity type, the substrate having a first doping concentration;
a non-volatile memory (NVM) device including:
a first well region of a second conductivity type disposed in the substrate;
a first body region of the first conductivity type disposed over the first well region;
a gate dielectric disposed on the first body region;
a first control gate disposed on the gate dielectric; and
first source and drain regions of the second conductivity type disposed in the first body region on opposite sides of the first control gate;
a second body region disposed in the first well region of the first conductivity type; and
a plate portion disposed over the second body region and being connected to the control gate, wherein the plate portion and second body region form a coupling capacitor, and
a bipolar transistor including:
a second well region of the second conductivity type disposed in the substrate;
a base region of the first conductivity type disposed in the second well region; and
an emitter region of the second conductivity type disposed in the base region,
wherein the first body region and the second body region of the NVM device and the base region of the bipolar transistor have a substantially identical doping concentration.
11. The BiCMOS IC according to claim 10 , wherein the first source and drain regions of the NVM device and the emitter region of the bipolar transistor have a substantially identical doping concentration.
12. The BiCMOS IC according to claim 10 , further comprising a CMOS transistor CMOS field-effect transistor (FET), the CMOS FET including:
a third well region of the first conductivity type disposed in the substrate;
a second control gate disposed over the third well region; and
second source and drain regions of the second conductivity type disposed in the third well region on opposite sides of the control gate,
wherein the first control gate of the NVM device and the second control gate of the CMOS FET have a substantially identical conductivity.
13. The BiCMOS IC according to claim 12 ,
wherein the NVM device further includes a first gate dielectric disposed between the first control gate and the substrate,
wherein the CMOS FET further includes a second gate dielectric disposed between the second control gate and the substrate, and
wherein the second gate dielectric of the CMOS FET and the first gate dielectric have a substantially identical thickness and composition.