Pseudo ternary content addressable memory device having row redundancy and method therefor
View Patent ↗A pseudo ternary content addressable memory (PTCAM) device ( 100 ) can include a number of PTCAM blocks ( 102 - 0 to 102 - 63 ), each of which can include a number of standard PTCAM rows ( 106 - 0 to 106 - 63 ) and a standard memory row ( 104 - 0 to 104 - 63 ) for storing and providing mask information for the PTCAM rows. Redundancy for replacing a defective standard PTCAM row can be provided by a redundant section ( 108 ) that include fewer PTCAM rows than in a PTCAM block ( 102 - 0 to 102 - 63 ). Non-defective PTCAM rows within a standard PTCAM block containing a defective PTCAM row can continue to operate.
1. A pseudo ternary content addressable memory (PTCAM) device, comprising:
at least m memory cell rows, where m is an integer of at least one, each memory cell row providing mask data that selectively inhibits bit comparison operations within n corresponding PTCAM rows, where n is an integer greater than one; and
at least p redundant memory cell rows, where p is an integer of at least one, each redundant memory cell row providing mask data that selectively inhibits bit comparison operations within q corresponding redundant PTCAM rows, where q is less than n, each redundant PTCAM row having store circuits that store a multi-bit data value and compare circuits that compare the stored data value to a compare data value.
2. The PTCAM device of claim 1 , wherein:
each m memory cell row provides mask data to at least eight PTCAM rows.
3. The PTCAM device of claim 1 , wherein:
each memory cell row and redundant memory cell row comprises static random access memory (SRAM) cells.
4. The PTCAM device of claim 1 , further including:
at least one wordline commonly connected to one of the at least m memory cell rows and one of the at least p redundant memory cell rows that provides essentially simultaneous access to said at least one memory cell row and at least one redundant memory cell row in read and write operations to said memory cell rows.
5. The PTCAM device of claim 1 , wherein:
p is an integer greater than one, and each redundant memory cell row provides mask data that selectively inhibits bit comparison operations within one corresponding redundant PTCAM row.
6. The PTCAM device of claim 1 , wherein:
the at least m memory cell rows are arranged into a plurality of PTCAM arrays, each comprising a plurality of memory cell rows and a group of PTCAM rows corresponding to each memory cell row; and
the q redundant PTCAM rows are replacement rows for PTCAM rows in any of the PTCAM arrays.
7. A method of providing redundant pseudo ternary content addressable memory cell (PTCAM) rows, comprising the steps of:
disabling a defective PTCAM row within a group of PTCAM rows, each PTCAM row of the group receiving mask information from a row of memory cells;
accessing the row of memory cells and a row of redundant memory cells essentially simultaneously to write mask into both such rows, the row of redundant memory cells providing the mask information to at least one redundant PTCAM row; and
storing data values in the redundant PTCAM row to replace the defective PTCAM row while retaining the operation of the other PTCAM rows of the group.
8. The method of claim 7 , wherein:
accessing the row of memory cells and the row of redundant memory cells includes commonly activating at least one wordline in the row of memory cells and the row of redundant memory cells.
9. The method of claim 7 , wherein:
the row of memory cells and a row of redundant memory cells comprise static random access memory (SRAM) cells.
10. The method of claim 7 , further including:
in a compare operation,
providing a mask value from the row of memory cells to the group of PTCAM rows,
providing the mask value from the row of redundant memory cells to the redundant PTCAM row, and
providing a compare data value to at least the non-defective PTCAM rows of the group of PTCAM rows and to the redundant PTCAM row.
11. The method of claim 7 , wherein:
disabling the defective PTCAM row includes changing the state of at least one fuse-type device.
12. The method of claim 7 , wherein:
accessing the row of memory cells and a row of redundant memory cells essentially simultaneously includes changing the state of a plurality of fuse-type devices.
13. A content addressable memory (CAM) device, comprising:
a plurality of regular array sections, each regular array section comprising a plurality of regular PTCAM rows that match stored data values against received compare data values, and at least one standard mask row that provides mask data to the regular PTCAM rows of the regular array section, the mask data selectively masking matching within the PTCAM rows; and
at least one redundant array section comprising at least one redundant PTCAM row and at least one redundant mask row that provides the mask data to the at least one redundant PTCAM row, the mask data selectively masking matching within the at least one redundant PTCAM row; wherein
the number redundant PTCAM rows of each redundant array section is less than the number regular PTCAM rows in each regular array section.
14. The CAM device of claim 13 , wherein:
each regular PTCAM row and redundant PTCAM row comprises a plurality of PTCAM cells, each PTCAM cell having a store circuit and a compare circuit, the compare circuit having a first input coupled to receive a stored data value bit from the store circuit, a second input coupled to receive a compare data value, and a third input coupled to receive a mask data value.
15. The CAM device of claim 14 , wherein:
each regular PTCAM row comprises no less than 36 PTCAM cells; and
the at least one redundant PTCAM row comprises no less than 36 PTCAM cells.
16. The CAM device of claim 13 , wherein:
each regular mask row comprises a plurality of memory cells commonly coupled to a word line; and
the at least one redundant mask row comprises a plurality of memory cells commonly coupled to the word line.
17. The CAM device of claim 16 , wherein:
each regular array section comprises at least 2 N regular PTCAM rows, where N is an integer greater than one and one standard mask row; and
each redundant array section comprises one redundant PTCAM row and one standard mask row.
18. The CAM device of claim 17 , wherein:
the integer N is three.
19. The CAM of claim 13 , wherein:
the at least one standard mask row comprises a plurality of static random access memory (SRAM) cells; and
the at least one redundant mask row comprises a plurality of SRAM cells; wherein
each SRAM cell comprises a latch circuit that stores complementary bit values at latch nodes, at least one node being coupled to a bit line.
20. The CAM of claim 13 , wherein:
the number of regular array sections is N, each regular array section comprises X regular PTCAM rows, and one standard mask row; and
the at least one redundant array section includes N redundant array sections, each comprising at least one redundant PTCAM row and one redundant mask row.