Semiconductor integrated circuit for high-speed, high-frequency signal transmission

1. A semiconductor integrated circuit comprising:

a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other at a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and

a wiring structure which is formed to apply differential signals to respective gates of said pair of MOS transistors and to apply a common potential to respective source diffusion layers of said pair of MOS transistors;

wherein a part of the well is disposed between said respective drain diffusion layers of said pair of MOS transistors, and none of said respective source diffusion layers of said pair of MOS transistors is disposed between said respective drain diffusion layers.

2. A semiconductor integrated circuit according to claim 1 , wherein said pair of MOS transistors are arranged adjacent to each other with a distance such that a transit time of charges by said charge exchange between said drain diffusion layers is smaller than a transition time during phase inversion of said differential signals.

3. A semiconductor integrated circuit according to claim 1 , wherein said pair of MOS transistors are arranged adjacent to each other so that sides of said drain diffusion layers along a gate width direction are opposed to each other.

4. A semiconductor integrated circuit according to claim 3 , wherein a plurality of pairs of MOS transistors is arranged in the same well, and gates, drains and sources therof are mutually connected respectively.

5. A semiconductor integrated circuit according to claim 1 , wherein said wiring structure is formed by connecting a paired structure of transmission line composed of two lines which transmit differential signals.

6. A semiconductor integrated circuit according to claim 5 , wherein characteristic impedance of said paired structure of transmission line is determined in a range of 50 to 200Ω.

7. A semiconductor integrated circuit according to claim 5 or 6 , wherein a relationship

2 a≦b

is satisfied where a is a distance between one line and the other line of said paired structure of transmission line, and b is a distance between said paired structure of transmission line and another paired structure of transmission line adjacent to said paired structure of transmission line.

8. A semiconductor integrated circuit comprising:

a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other at a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and

a wiring structure which is formed to apply differential signals to respective gates of said pair of MOS transistors and to apply a common potential to respective sources of said pair of MOS transistors; and

a differential circuit comprised of said pair of MOS transistors,

wherein in said wiring structure, differential input signals include a positive signal and an inverted signal, said positive signal is applied to one gate of said pair of MOS transistors, said inverted signal is applied to the other gate of said pair of MOS transistors, and differential output signals are output from said drain diffusion layer of each of said pair of MOS transistors;

and in addition to said pair of MOS transistors, one or more other MOS transistors are formed in the same well and are arranged with a distance such that interference due to said charge exchange between said drain diffusion layers of said pair of MOS transistors and drain diffusion layers of said other MOS transistors does not occur.

9. A semiconductor integrated circuit according to claim 8 , wherein said pair of MOS transistors are arranged to satisfy a relationship

1.5 ×d≦k

where d is a distance between said drain diffusion layers of said pair of MOS transistors, and k is a minimum distance between said drain diffusion layers of said pair of MOS transistors and drain diffusion layers of said other MOS transistors.

10. A semiconductor integrated circuit comprising:

a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and

a wiring structure which is formed so that a termination resistor circuit is configured using on-resistances of respective said pair of MOS transistors on a first line and a second line which transmit differential signals, and said first line is connected to one of said drain diffusion layers of said pair of MOS transistors, while said second line is connected to the other one of said drain diffusion layers of said pair of MOS transistors.

11. A semiconductor integrated circuit comprising:

a pair of diffusion layer resistances which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange therebetween is possible; and

a wiring structure which is formed so that a termination resistor circuit is configured using said pair of diffusion layer resistances on a first line and a second line which transmit differential signals, and said first line is connected to one of said diffusion layer resistances, while said second line is connected to the other one of said diffusion layer resistances.