Accurate temperature measurement method for low beta transistors
View Patent ↗An accurate temperature monitoring system that uses a precision current control circuit to apply accurately ratioed currents to a semiconductor device, which may be a bipolar junction transistor (BJT), used for sensing temperature. A change in base-emitter voltage (ΔV BE ) proportional to the temperature of the BJT may be captured and provided to an ADC, which may generate a numeric value corresponding to that temperature. The precision current control circuit may be configured to generate a reference current, capture the base current of the BJT, generate a combined current equivalent to a sum total of the base current and a multiple of the reference current, and provide the combined current to the emitter of the BJT. In response to this combined current, the collector current of the BJT will be equivalent to the multiple of the reference current. The ratios of the various collector currents conducted by the BJT may thus be accurately controlled, leading to more accurate temperature measurements.
1. A method for controlling current in a semiconductor device, the method comprising:
generating a reference current;
capturing a control current flowing through a control terminal of the semiconductor device;
summing the control current with a multiple of the reference current to obtain an input current; and
applying the input current to an input terminal of the semiconductor device;
wherein in response to said applying the input current, a device current flowing through an output terminal of the semiconductor device is equivalent to the multiple of the reference current.
2. The method of claim 1 , wherein said capturing the control current comprises:
applying the control current to an input terminal of a first transistor; and
mirroring the control current in a second transistor to obtain a first mirror current flowing through an input terminal of the second transistor, wherein the first mirror current is equivalent to the control current.
3. The method of claim 2 , wherein said summing the control current with the multiple of the reference current comprises:
capturing an output current flowing through an output terminal of a third transistor, wherein the output current is a sum of the first mirror current and the reference current; and
mirroring the output current in a fourth transistor to obtain a second mirror current flowing through an output terminal of the fourth transistor, wherein the second mirror current is equivalent to the output current.
4. The method of claim 3 , wherein said applying the input current to the input terminal of the semiconductor device comprises applying the second mirror current to the input terminal of the semiconductor device.
5. The method of claim 1 , wherein the multiple of the reference current is equivalent to the reference current multiplied by N.
6. The method of claim 1 , wherein each component current of the N component currents is equivalent to the control current divided N.
7. The method of claim 1 , wherein said capturing the control current further comprises mirroring the at least one component current in a second transistor to obtain a first mirror current flowing through an input terminal of the second transistor, wherein the first mirror current is equivalent to the at least one component current.
8. The method of claim 7 , wherein said summing the control current with the multiple of the reference current comprises:
capturing an output current flowing through an output terminal of a third transistor, wherein the output current is a sum of the first mirror current and the reference current; and
mirroring the output current in each one of N output mirror transistors to obtain N component mirror currents, each one of the N component mirror currents flowing through a corresponding output terminal of a respective one of the N output mirror transistors, wherein each one of the N component mirror currents is equivalent to the output current; and
summing the N component mirror currents to obtain a total mirror current.
9. The method of claim 8 , wherein said applying the input current to the input terminal of the semiconductor device comprises applying the total mirror current to the input terminal of the semiconductor device.
10. The method of claim 8 , wherein said generating the reference current comprises adjusting the reference current to bring the total mirror current to an optimum value, wherein the optimum value represents a maximum total mirror current at which each one of the N output mirror transistors still operates in saturation mode.
11. The method of claim 10 , wherein said adjusting the reference current comprises:
setting the reference current to an initial value to obtain the output current;
monitoring the output current;
incrementing the reference current by a specified amount; and
performing said incrementing a plurality of times until the output current exceeds a predetermined value.
12. The method of claim 11 , wherein said adjusting the reference current farther comprises decrementing the reference current by the specified amount following the output current having exceeded the predetermined value.
13. A system for controlling current in a semiconductor device, the system comprising:
a first circuit configured to generate a reference current;
a second circuit coupled to the first circuit, and operable to receive a control current flowing through a control terminal of the semiconductor device; and
a third circuit coupled to the first circuit and to the second circuit, and operable to generate a combined current equivalent to a sum total of the control current and a multiple of the reference current, and further operable to provide the combined current to an input terminal of the semiconductor device;
wherein, in response to the combined current being applied to the input terminal of the semiconductor device, a device current flowing through an output terminal of the semiconductor device is equivalent to the multiple of the reference current.
14. The system of claim 13 , wherein the second circuit is operable to generate a first mirror current equivalent to one of:
the control current; and
the control current divided by a specified value (N);
wherein the second circuit is operable to provide the first mirror current to the third circuit.
15. The system of claim 14 , wherein the third circuit is operable to conduct a sum current comprising a sum total of the first mirror current and the reference current.
16. The system of claim 15 , wherein the third circuit is operable to generate one of:
a second mirror current equivalent to the sum current, wherein the combined current comprises the second mirror current; and
N component mirror currents, wherein each one of the N component mirror currents is equivalent to the sum current, and wherein the combined current comprises a sum total of the N component mirror currents.
17. The system of claim 14 , wherein the second circuit is operable to split the control current into N equal-size component currents, wherein the first mirror current is equivalent to one of the N equal-size component currents.
18. The system of claim 13 , wherein the first circuit is operable to adjust the reference current to maximize the combined current without the combined current exceeding a specified value.
19. The system of claim 18 , wherein the first circuit is operable to adjust the reference current when the combined current is equivalent to a sum total of the control current and the reference current, to maximize the combined current without the combined current exceeding a specified value.
20. The system of claim 18 , wherein the first circuit comprises a digital control block operable to set the reference current to one of a plurality of specified values.
21. The system of claim 20 , wherein the digital control block comprises a plurality of control outputs;
wherein the first circuit further comprises a plurality of parallel-coupled transistors, a respective input terminal of each of the plurality of parallel-coupled transistors switchably coupled to a respective one of the plurality of control outputs;
wherein the reference current comprises a sum total of a plurality of individual currents, each of the plurality of individual currents flowing into the respective input terminal of a respective one of the plurality of parallel-coupled transistors.
22. The system of claim 20 , wherein the digital control block is configured to receive a detection current from the third circuit;
wherein the digital control block is operable to set the reference current to an initial value and increment the reference current until the detection current exceeds the specified value.
23. The system of claim 22 , wherein the digital control block is operable to increment the reference current in discrete steps, and decrement the reference current by a single discrete step in response to the detection current exceeding the specified value.
24. The system of claim 13 , wherein the first circuit and the second circuit comprise NMOS devices and PMOS devices.
25. A temperature monitoring system comprising:
a semiconductor device having a defined, generally non-linear input-output characteristic that varies with temperature; and
a current control circuit configured to couple to the semiconductor device and comprising:
a first circuit configured to generate a reference current;
a second circuit configured to couple to the first circuit, and operable to receive a control current flowing through a control terminal of the semiconductor device; and
a third circuit configured to couple to the first circuit and to the second circuit, and operable to conduct a combined current equivalent to a sum total of the control current and a multiple of the reference current, and further operable to provide the combined current to an input terminal of the semiconductor device;
wherein, in response to the combined current being applied to the input terminal of the semiconductor device, a device current flowing through an output terminal of the semiconductor device is equivalent to the multiple of the reference current.
26. The temperature monitoring system of claim 25 , further comprising an analog-to-digital converter (ADC) configured to couple to the semiconductor device;
wherein in response to the combined current being applied to the input terminal of the semiconductor device, the semiconductor device is operable to develop an output voltage across its input terminal and control terminal;
wherein the output voltage has a respective value corresponding to each different multiple of the reference current;
wherein the ADC is operable to produce a numeric value corresponding to a temperature of the semiconductor device in response to at least two different respective values of the output voltage.
27. The system of claim 26 , wherein the semiconductor device comprises a PN-junction, and wherein the control terminal and the input terminal correspond to terminals of the PN-junction.
28. The system of claim 27 , wherein the output voltage comprises a base-emitter voltage developed across the PN-junction.
29. The system of claim 27 , wherein the PN-junction is comprised in a bipolar junction transistor (BJT), wherein the control terminal is the base of the BJT and the input terminal is the emitter of the BJT.
30. The system of claim 26 , wherein the ADC is one of:
a pipeline ADC;
a cyclic ADC;
a delta-sigma ADC;
a successive approximation ADC; and
an integrating ADC.
31. A method for controlling current in a semiconductor device, the method comprising:
obtaining a control current based on a first device current flowing through a control terminal of the semiconductor device, wherein a value of the control current is equal to a value of the first device current divided by N, wherein N is an integer greater than or equal to 1;
generating a mirrored instance of the control current at a first node;
applying a first current to the first node to obtain a sum current comprising a sum of the mirrored instance of the control current and the first current;
generating N mirrored instances of the sum current at a second node coupled to an input terminal of the semiconductor device; and
generating a second device current flowing through an output terminal of the semiconductor device, wherein in response to said mirroring the sum current, a value of the second device current is equal to N times a value of the first current.
32. The method of claim 31 , wherein said obtaining the control current comprises splitting the first device current into N component currents, wherein a value of at least one of the N component currents is equal to the value of the first device current divided by N, wherein the control current is the at least one of the N component currents.
33. The method of claim 31 , wherein said applying the first current comprises:
generating a reference current; and
generating a mirrored instance of the reference current at the first node, wherein the mirrored instance of the reference current is the first current.
34. A system for controlling a first device current flowing through an output terminal of a semiconductor device, the system comprising:
a first node configured to couple to an input terminal of the semiconductor device;
a second node configured to receive a reference current;
a second circuit configured to:
receive a second device current flowing through a control terminal of the semiconductor device;
generate a control current based on the second device current, wherein a value of the control current is equal to a value of the second device current divided by N, wherein N is an integer greater than or equal to 1; and
generate a mirrored instance of the control current at the second node to obtain a sum current comprising a sum of the mirrored instance of the control current and the reference current; and
a third circuit configured to:
receive the sum current; and
generate N mirrored instances of the sum current at the first node to adjust the second device current to have a value equal to N times a value of the reference current.
35. The system of claim 34 , wherein the second circuit is configured to:
split the second device current into N component currents, wherein a value of at least one of the N component currents is equal to the value of the second device current divided by N, wherein the control current is the at least one of the N component currents.
36. The system of claim 34 , further comprising a current source configured to generate the reference current.
37. The system of claim 34 , further comprising:
a current source configured to generate a first current; and
a fourth circuit configured to generate a mirrored instance of the first current at the second node, wherein the mirrored instance of the first current is the reference current.