Magnetic Memory Array

1. A magnetic memory array comprising:

a plurality of cell columns;

a pair of reference cell columns, including a first reference cell column and a second reference cell column;

a comparator with a first and a second input terminal; and a switching circuit configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and the switching circuit is further configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.

2. The memory array of claim 1 , comprising:

wherein the magnetic memory array comprises an array of magnetoresistive random access rotational switching memory cells.

3. The memory array of claim 1 , comprising:

a plurality of current lines each series connected to a single one of the memory cells and a single control transistor having a control terminal in a single ended configuration to form the cell columns.

4. The memory array of claim 3 , comprising wherein a pair of the cell columns are provided as the pair of reference cell columns to provide reference signal outputs.

5. The memory array of claim 1 , comprising:

a select line being series connected to the control terminals of the control transistors.

6. The memory array of claim 1 , comprising:

an output circuit defined by the comparator and the switching circuit.

7. The memory array of claim 1 , wherein the output circuit comprises a sense amplifier.

8. The memory array of claim 1 , comprising:

an offset current generation circuit configured to apply a predetermined offset current to the output circuit.

9. A magnetic memory array comprising:

a plurality of cell columns;

a pair of reference cell columns, including a first reference cell column and a second reference cell column; and

an output circuit comprising a comparator with a first and a second input terminal, and a switching circuit configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.

10. The memory array of claim 9 , wherein the output circuit comprises a sense amplifier.

11. The memory array of claim 10 , comprising:

an offset current generation circuit configured to apply a predetermined offset current to the output circuit.

12. The memory array of claim 11 , comprising:

wherein the magnetic memory array comprises an array of magnetoresistive random access rotational switching memory cells.

13. The memory array of claim 12 , comprising:

a plurality of current lines each series connected to a single one of the memory cells and a single control transistor having a control terminal in a single ended configuration to form the cell columns.

14. The memory array of claim 13 , comprising wherein a pair of the cell columns are provided as the pair of reference cell columns to provide reference signal outputs.

15. The memory array of claim 14 , comprising:

a select line being series connected to the control terminals of the control transistors.

16. An array of magnetoresistive random access rotational switching memory cells comprising:

a plurality of current lines each of which being series connected to a single one of the memory cells and a single control transistor having a control terminal in a single ended configuration to form cell columns, a pair of the cell columns being provided as reference cell columns to provide reference signal outputs;

a select line being series connected to the control terminals of the control transistors; and

an output circuitry having a comparator with a first and a second input terminal and switching circuitry coonfigured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, so as to differentially compare output signals from the different cell columns, the switching circuitry further being configured to connect a first one of the pair of reference cell columns to the first input terminal and a second one of the pair of reference cell columns to the second input terminal.

17. The magnetic random access memory array of claim 16 , wherein said output circuitry is a sense amplifier.

18. The magnetic random access memory array of claims 16 , further comprising:

an offset current generation means connected to the output circuitry for applying a predetermined offset current to the output circuitry.

19. A method for programming rotational switching cells of reference columns in an array of magnetoresistive random access rotational switching memory cells comprising:

connecting a first reference cell column to a first input terminal of a comparator and a second reference cell column to a second input terminal of the comparator for sensing logic states of the rotational switching cells connected therewith; and

applying currents to conductive lines magnetically coupled to the rotational switching cells of the reference columns for generating a synthetic magnetic field to perform at least one toggle switching of the rotational switching cells in response to an output of an output circuitry.

20. The method of claim 19 , further comprising:

applying an offset current to said output circuitry.

21. A method for programming rotational switching cells of reference columns in an array of magnetoresistive random access rotational switching memory cells comprising:

defining a plurality of current lines each of which being series connected to a single one of the memory cells and a single control transistor having a control terminal in a single ended configuration to form cell columns, a pair of the cell columns being provided as reference cell columns to provide reference signal outputs;

providing a select line being seriesly connected to the control terminals of the control transistors;

an output circuitry having a comparator with a first and a second input terminal and switching circuitry adapted to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, so as to differentially compare output signals from the different cell columns, the switching means further being configured to connect a first one of the pair of reference cell columns to the first input terminal and a second one of the pair of reference cell columns to the second input terminal;

connecting the first one of the reference cell columns to the first input terminal of the comparator and the second one of the reference cell columns to the second input terminal for sensing the logic states of the rotational switching cells connected therewith; and

applying currents to conductive lines magnetically coupled to the rotational switching cells of the reference columns for generating a synthetic magnetic field to perform at least one toggle switching of the rotational switching cells in response to an output of the output circuitry.

22. The method of claim 21 , further comprising:

applying an offset current to said output circuitry.

23. A magnetic memory array comprising:

a plurality of cell columns;

a pair of reference cell columns, including a first reference cell column and a second reference cell column;

means for comparing with a first and a second input terminal; and means for switching configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and the means for switching is further configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.