Granted Patent B2

US 7,232,735 · App. 11/289,336 · Granted Jun 19, 2007

Abstract

Claims (21)

1. A method for manufacturing a semiconductor device including a cylindrical capacitor, comprising the steps of:

boring a capacitor hole for the cylindrical capacitor;

forming a silicon layer including a lower high-concentration impurity sublayer and an upper low-concentration impurity sublayer on the wall of the capacitor hole, the lower high-concentration impurity sublayer containing a high concentration of impurities and the upper low-concentration impurity sublayer containing a low concentration of impurities;

etching the silicon layer;

and roughening the surface of the silicon layer with a hemispherical silicon grain treatment after etching; wherein

the upper low-concentration impurity sublayer on the bottom of the capacitor hole is completely etched away and the upper low-concentration impurity sublayer in a lower region of the capacitor hole is partly etched away in the etching step.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the thickness of a residual silicon layer on the bottom of the capacitor hole in the etching step is controlled by monitoring a change in plasma emission generated by the etching of the silicon layer on the top surface of the capacitor hole to determine an etching end point.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the etching rate of silicon on the top surface of the capacitor hole is higher than the etching rate of silicon on the bottom of the capacitor hole in the etching step.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the hemispherical silicon grains on the bottom of the capacitor hole are smaller in crystal grain size than those in an upper region of the capacitor hole in the roughening step.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the silicon layer is etched by anisotropic etching.

6. A semiconductor device including a cylindrical capacitor formed in an insulating film, wherein

the bottom of a cylinder for the cylindrical capacitor has an opening area smaller than that of the top surface of the cylinder,

the cylinder has hemispherical silicon grains on the wall, and

the hemispherical silicon grains on the bottom of the cylinder are smaller in crystal grain size than those in an upper region of the cylinder; wherein

the cylinder has a lower region of an inclined sidewall between the upper region and the bottom, and the hemispherical silicon grains formed in the lower region are smaller in crystal grain size than the hemispherical silicon grains formed in the upper region and are larger in crystal grain size than the hemispherical silicon grains formed on the bottom.

7. The semiconductor device according to claim 6 , wherein

a silicon foundation layer is formed on the wall of the cylinder, and

the thickness of the silicon foundation layer on the bottom of the cylinder is smaller than that in the upper region of the cylinder.

8. The semiconductor device according to claim 6 , wherein the insulating film comprises a silicon oxide system insulating film made of a material selected from the group of silicon oxide, a boron phosphorous silicate glass, a phosphorous silicate glass, a non-doped silicate glass, a boron silicate glass, a spin-on glass, and silicon oxide nitride and a nitride film.

9. The semiconductor device according to claim 6 , comprising the cylindrical capacitor as a memory cell.

10. The semiconductor device according to claim 9 , wherein the semiconductor device is a dynamic random access memory.

Assignments (8)