Semiconductor device comprising a memory portion and a peripheral circuit portion
View Patent ↗The present invention provides a semiconductor chip that provides a semiconductor device with high reliability and low leak current, and a method of manufacturing such a semiconductor chip, and more specifically, provides a semiconductor chip comprising memory portions and a peripheral circuit portion, where the memory portions and the peripheral circuit portion are formed in a main surface portion of the semiconductor chip, a thickness of the sections of the semiconductor chip passing through the main surface portion in which the memory portions are formed is larger than a thickness of sections of the semiconductor chip passing through the main surface portion in which the peripheral circuit portion is formed, and a method of manufacturing such a semiconductor chip.
1. A semiconductor device including a board and a semiconductor chip mounted on the board, wherein the semiconductor chip is formed from a semiconductor material, and comprises memory portions and a peripheral circuit portion including predetermined portions that are adjacent to respective memory portions, wherein
the memory portions and the peripheral circuit portion are formed in a main surface portion of the semiconductor chip, and
the semiconductor chip further comprising groove portions that are formed in the semiconductor material on a backside of the semiconductor chip only at positions corresponding to the projected plan of the peripheral circuit portion except the predetermined portions and that have a depth in which the groove portions do not reach an element of a peripheral circuit in the peripheral circuit portion, said backside opposing said main surface.
2. The semiconductor device according to claim 1 , further comprising flat portions that are formed on the backside of the semiconductor chip at positions corresponding to the projected plan of the memory portions and the predetermined portions.
3. The semiconductor device according to claim 1 , wherein a depth of the groove portions is in a range of 5 to 60% of the thickness of the semiconductor chip.
4. The semiconductor device according to claim 1 , wherein the semiconductor chip is bonded to the board.
5. The semiconductor device according to claim 1 or 4 , wherein at least one of a surface of the semiconductor chip comes into contact with a sealing resin.