Analog-to-digital converter with non-linearity compensation

1. An analog-to-digital converter (ADC) for converting an analog input value to an output digital code, the ADC comprising:

a first ADC configured to receive the analog input value and to convert the analog input value to a first digital code;

a first digital-to-analog converter (DAC) configured to convert the first digital code to a first analog value;

a first linearization module configured to receive the first digital code and to produce a first linear-correction code;

a second ADC configured to receive a remainder portion of the analog input value and to convert the remainder portion to a second digital code, wherein the remainder portion comprises a difference between the analog input value and the first analog value, and wherein the second ADC has a full-scale range that is greater than the remainder portion;

a second linearization module configured to receive the second digital code and to produce a second linear-correction code; and

an accumulator configured to combine the first linear-correction code and the second linear-correction code to produce the output digital code, wherein the remainder portion includes a quantization error contributed from the first ADC and non-linearity errors contributed from the first ADC, from the first DAC, and from a subtractor that computes the remainder portion, the first linear-correction code directly compensating for non-linearity errors contributed from the first DAC and the subtractor.

2. The system of claim 1 , wherein the second linear-correction code is approximately equal to a previously measured analog input voltage value of the second ADC, the previously measured analog input voltage value corresponding to the second digital code.

3. The system of claim 1 , wherein:

the first linearization module comprises a first lookup table coupled to an output of the first ADC; and

the second linearization module comprises a second lookup table coupled to an output of the second ADC.

4. The system of claim 3 , wherein each of the first and second lookup tables is a two-dimensional lookup table indexed by a previous code and by a current code, wherein each lookup table is configured to produce a linear-correction code corresponding to the previous code and the current code.

5. The system of claim 1 , wherein the first linearization module comprises a two-dimensional lookup table coupled to an output of the first ADC, wherein the two-dimensional lookup table stores a third linear-correction code that corresponds to the first digital code when the first ADC transitions to the first digital code from a higher code; and wherein the two-dimensional lookup table stores a fourth linear-correction code that corresponds to the first digital code when the first ADC transitions to the first digital code from a lower code; wherein the first linearization module is further configured to:

compare the first digital code to a previous digital code produced by the first ADC;

determine that the analog input value is increasing; and

select the third linear-correction code to be the first linear-correction code.

6. The system of claim 1 , wherein the second linearization module comprises a two-dimensional lookup table coupled to an output of the second ADC, wherein the two-dimensional lookup table stores a third linear-correction code that corresponds to the second digital code when the second ADC transitions to the second digital code from a higher code; and wherein the two-dimensional lookup table stores a fourth linear-correction code that corresponds to the second digital code when the second ADC transitions to the second digital code from a lower code; wherein the second linearization module is further configured to:

compare the second digital code to a previous digital code produced by the second ADC;

determine that the remainder portion is decreasing; and

select the fourth linear-correction code to be the second linear-correction code.

7. The system of claim 1 , wherein the full-scale range of the second ADC is greater than one least-significant bit of the first DAC.

8. The system of claim 1 , wherein the first and second linear-correction codes comprise a most significant range and a least significant range, respectively, of the output digital code.

9. A method for converting an analog input value to an output digital code, the method comprising:

at a first analog-to-digital converter (ADC), receiving the analog input value and converting the analog input value to a first digital code;

at a first digital-to-analog converter (DAC), converting the first digital code to a first analog value;

at a first linearization module, receiving the first digital code and producing a first linear-correction correction code;

at a second ADC, receiving a remainder portion of the analog input value and converting the remainder portion to a second digital code, wherein the remainder portion comprises a difference between the analog input value and the first analog value;

wherein a full-scale range of the second ADC is at least as large as the remainder portion, and wherein the remainder portion includes a quantization error contributed from the first ADC and non-linearity errors contributed from the first ADC, from the first DAC, and from a subtractor that computes the remainder portion, the first linear-correction code directly compensating for non-linearity errors contributed from the first DAC and from the subtractor;

at a second linearization module, receiving the second digital code and producing a second linear-correction code; and

combining the first linear-correction code and the second linear-correction code to produce the output digital code.

10. The method of claim 9 , wherein the second linear-correction code is approximately equal to a previously measured analog input voltage value of the second ADC, the previously measured analog input voltage value corresponding to the second digital code; and wherein the accumulator is configured to sum the first linear-correction code and the second linear-correction code to produce the output digital code.

11. The method of claim 9 , further comprising:

storing, in a two-dimensional lookup table, a third linear-correction code that corresponds to the first digital code when the first ADC transitions to the first digital code from a higher code;

storing, in the two-dimensional lookup table, a fourth linear-correction code that corresponds to the first digital code when the first ADC transitions to the first digital code from a lower code.

comparing the first digital code to a previous digital code produced by the first ADC;

determining that the analog input value is increasing; and

selecting the third linear-correction code to be the first linear-correction code.

12. The method of claim 9 , further comprising:

storing, in a two-dimensional lookup table, a third linear-correction code that corresponds to the second digital code when the second ADC transitions to the second digital code from a higher code;

storing, in the two-dimensional lookup table, a fourth linear-correction code that corresponds to the second digital code when the second ADC transitions to the second digital code from a lower code;

comparing the second digital code to a previous digital code produced by the second ADC;

determining that the remainder portion is decreasing; and

selecting the fourth linear-correction code to be the second linear-correction code.

13. The method of claim 9 , further comprising:

indexing a two-dimensional lookup table by a previous code and by a current code; and

storing, in the two-dimensional lookup table, a linear-correction code corresponding to the previous code and the current code.

14. The method of claim 9 , wherein the full-scale range is greater than one least-significant bit of the first DAC.

15. The method of claim 9 , further comprising selecting the first and second linear-correction codes to comprise a most significant range and a least significant range, respectively, of the output digital code.

16. The method of claim 9 , wherein combining the first and second linear-correction codes comprises summing the first and second linear-correction codes.

17. An analog-to-digital converter (ADC) for converting an analog input value to an output digital code, the ADC comprising:

a first ADC configured to receive the analog input value and to convert the analog input value to a first digital code;

a digital-to-analog converter (DAC) coupled to the output of the first ADC and configured to convert the first digital code to a first analog value;

a first two-dimensional lookup table coupled to the output of the first ADC and configured to receive the first digital code and to store first and second linear-correction codes that are approximately equal to first and second analog output voltage values measured previously for the DAC in response to the first two-dimensional lookup table receiving the first digital code, wherein the first two-dimensional lookup table is configured to:

compare the first digital code to a previous code produced by the first ADC;

select the first linear-correction code if the first digital code is larger than the previous code; and

select the second linear-correction code if the first digital code is less than the previous code;

a subtractor coupled to the output of the DAC and configured to subtract the first analog value from the analog input value to produce a remainder value;

a second ADC coupled to the output of the subtractor and configured to convert the remainder value to a second digital code;

a second two-dimensional lookup table coupled to the ouput of the second ADC and configured to receive the second digital code and to store third and fourth linear-correction codes that are approximately equal to third and fourth analog input voltage values measured previously for the second digital code, wherein the second two-dimensional lookup table is configured to:

compare the second digital code to a previous code produced by the second ADC;

select the third linear-correction code if the second digital code is larger than the previous code; and

select the fourth linear-correction code if the second digital code is less than the previous code; and

an accumulator configured to combine one of the first and second linear-correction codes and one of the third and fourth linear-correction codes to produce the output digital code.

18. An analog-to-digital converter (ADC) for converting an analog input value to an output digital code, the ADC comprising:

a first analog-to-digital converter configured to receive the analog input value and to convert the analog input value to a first digital code;

a first digital-to-analog converter (DAC) configured to convert the first digital code to a first analog value;

a first linearization module configured to receive the first digital code and to produce a first linear-correction code that is approximately equal to the first analog value, wherein the first linearization module stores linear-correction codes previously determined by measuring output values produced by the first DAC in response to receiving multiple digital input values, the linear-correction codes including the first linear-correction code;

a second ADC configured to receive a remainder portion of the analog input value and to convert the remainder portion to a second digital code, wherein the remainder portion comprises a difference between the analog input value and the first analog value;

a second linearization module configured to receive the second digital code and to produce a second linear-correction code; and

an accumulator configured to combine the first linear-correction code and the second linear-correction code to produce the output digital code.

19. A method for converting an analog input value to a multi-stage analog-to-digital converter (ADC) to an output digital code, the method comprising:

at a first ADC internal to the multi-stage ADC, receiving the analog input value and converting the analog input value to a first digital code;

at a first digital-to-analog converter (DAC) internal to the multi-stage ADC, converting the first digital code to a first analog value;

at a first linearization module, receiving the first digital code and producing a first linear-correction code that is approximately equal to the first analog value, wherein the first linearization module stores linear-correction codes previously determined by measuring output values produced by the first DAC in response to receiving multiple digital input values, the linear-correction codes including the first linear-correction code;

at a second ADC internal to the multi-stage ADC, receiving a remainder portion of the analog input value and converting the remainder portion to a second digital code, wherein the remainder portion comprises a difference between the analog input value and the first analog value;

at a second linearization module, receiving the second digital code and producing a second linear-correction code; and

combining the first linear-correction code and the second linear-correction code to produce the output digital code.