Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same
View Patent ↗A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.
1. A semiconductor device having a recessed gate and asymmetric dopant regions, comprising:
a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other;
a gate insulating layer pattern disposed on the semiconductor substrate;
a gate stack disposed on the semiconductor substrate such that the gate stack is protruded from the surface of the semiconductor substrate while the gate stack fills the trench; and
first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.
2. The semiconductor device as set forth in claim 1 , wherein the gate stack comprises a gate conduction layer pattern and a gate metal layer pattern, which are stacked in consecutive order.
3. The semiconductor device as set forth in claim 1 , wherein the gate stack extends to the upper surface of the semiconductor substrate adjacent to the first and second sidewalls of the trench such that the gate stack partially overlaps with the first and second dopant regions.
4. The semiconductor device as set forth in claim 1 , wherein
the first dopant region is disposed at the upper part of the semiconductor substrate adjacent to the first sidewall of the trench, and
the second dopant region is disposed at the upper part of the semiconductor substrate adjacent to the second sidewall of the trench.
5. The semiconductor device as set forth in claim 4 , wherein
the first dopant region is a source region, and
the second dopant region is a drain region.
6. The semiconductor device as set forth in claim 4 , wherein
the first dopant region is a drain region, and
the second dopant region is a source region.
7. The semiconductor device as set forth in claim 1 , wherein the first and second dopant regions have a lightly doped drain (LDD) structure.
8. The semiconductor device as set forth in claim 1 , further comprising:
a buffer insulation layer disposed on the exposed surface of the gate stack; and
a gate spacer layer disposed at the sidewall of the buffer insulation layer.